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An efficient STT-Ram last level cache architecture for GPUs
, Article Proceedings - Design Automation Conference ; 2-5 June , 2014 , pp. 1-6 ; ISSN: 0738100X ; ISBN: 9781479930173 ; Abbasitabar, H ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
Abstract
In this paper, having investigated the behavior of GPGPU applications, we present an effcient L2 cache architecture for GPUs based on STT-RAM technology. With the increase of processing cores count, larger on-chip memories are required. Due to its high density and low power characteristics, STT-RAM technology can be utilized in GPUs where numerous cores leave a limited area for on-chip memory banks. They have however two important issues, high energy and latency of write operations, that have to be addressed. Low data retention time STT-RAMs can reduce the energy and delay of write operations. However, employing STT-RAMs with low retention time in GPUs requires a thorough investigation on...