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    Soft error rate estimation of digital circuits in the presence of Multiple Event Transients (METs)

    , Article Proceedings -Design, Automation and Test in Europe, DATE, 14 March 2011 through 18 March 2011 ; March , 2011 , Pages 70-75 ; 15301591 (ISSN) ; 9783981080179 (ISBN) Fazeli, M ; Ahmadian, S. N ; Miremadi, S. G ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    2011
    Abstract
    In this paper, we present a very fast and accurate technique to estimate the soft error rate of digital circuits in the presence of Multiple Event Transients (METs). In the proposed technique, called Multiple Event Probability Propagation (MEPP), a four-value logic and probability set are used to accurately propagate the effects of multiple erroneous values (transients) due to METs to the outputs and obtain soft error rate. MEPP considers a unified treatment of all three masking mechanisms i.e., logical, electrical, and timing, while propagating the transient glitches. Experimental results through comparisons with statistical fault injection confirm accuracy (only 2.5% difference) and... 

    A low energy soft error-tolerant register file architecture for embedded processors

    , Article 11th IEEE High Assurance Systems Engineering Symposium, HASE 2008, Nanjing, 3 December 2008 through 5 December 2008 ; December , 2008 , Pages 109-116 ; 15302059 (ISSN); 9780769534824 (ISBN) Fazeli, M ; Ahmadian, S. N ; Miremadi, S. G ; Nanjing University; IEEE Computer Society; IEEE Reliability Society ; Sharif University of Technology
    2008
    Abstract
    This paper presents a soft error-tolerant architecture to protect embedded processors register files. The proposed architecture is based on selectively duplication of the most vulnerable registers values in a cache memory embedded beside the processor register file so called register cache. To do this, two parity bits are added to each register of the processor to detect up to three contiguous errors. To recover the erroneous register value, two distinct cache memories are utilized for storing the redundant copy of the vulnerable registers, one for short lived registers and the other one for long lived registers. The proposed method has two key advantageous as compared to fully ECC protected...