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    An efficient low-latency point-multiplication over curve25519

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 66, Issue 10 , 2019 , Pages 3854-3862 ; 15498328 (ISSN) Salarifard, R ; Bayat Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    The elliptic curve cryptography (ECC) has gained attention mainly due to its lower complexity compared to other asymmetric methods while providing the same security level. The most performance critical operation in ECC is the point multiplication. Thus, its efficient implementation is desirable. One of the most secure and lightweight ECC curves, which satisfies all standard security criteria, is the Curve25519. In this paper, a low latency Karatsuba-Ofman-based field multiplier (KOM) and an efficient point multiplication over Curve25519 have been proposed. The improvements have been achieved mainly due to the proposed low latency pipelined KOM and efficient scheduling of field operations.... 

    Lightweight and DPA-resistant post-quantum cryptoprocessor based on binary ring-LWE

    , Article 20th International Symposium on Computer Architecture and Digital Systems, CADS 2020, 19 August 2020 through 20 August 2020 ; 2020 Ebrahimi, S ; Bayat Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    With the exponential growth in the internet of things (IoT) applications such as smart city and e-health, more embedded devices and smart nodes are connected to the network. In order to provide security for such resource-constrained devices, different cryptographic schemes such as public key encryption (PKE) are required. However, considering the high complexity and vulnerability of classic PKE schemes against quantum attacks, it is necessary to consider other possible options. Recently, lattice-based cryptography and especially learning with errors (LWE) have gained high attention due to resistance against quantum attacks and relatively low-complexity operations. During the past decade,... 

    Lightweight and fault-resilient implementations of binary ring-lwe for iot devices

    , Article IEEE Internet of Things Journal ; Volume 7, Issue 8 , 2020 , Pages 6970-6978 Ebrahimi, S ; Bayat Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    While the Internet of Things (IoT) shapes the future of the Internet, communications among nodes must be secured by employing cryptographic schemes such as public-key encryption (PKE). However, classic PKE schemes, such as RSA and elliptic curve cryptography (ECC) suffer from both high complexity and vulnerability to quantum attacks. During the past decade, post-quantum schemes based on the learning with errors (LWEs) problem have gained high attention due to the lower complexity among PKE schemes. In addition to resistance against theoretical (quantum and classic) attacks, every practical implementation of any cryptosystem must also be evaluated against different side-channel attacks such... 

    PLCDefender: Improving remote attestation techniques for PLCs using physical model

    , Article IEEE Internet of Things Journal ; 2020 Salehi, M ; Bayat Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    In order to guarantee the security of industrial control system (ICS) processes, the proper functioning of the programmable logic controllers (PLCs) must be ensured. In particular, cyber-attacks can manipulate the PLC control logic program and cause terrible damage that jeopardize people’s life when bringing the state of the critical system into an unreliable state. Unfortunately, no remote attestation technique has yet been proposed that can validate the PLC control logic program using a physics-based model that demonstrates device behavior. In this paper, we propose PLCDefender, a mitigation method that combines hybrid remote attestation technique with a physics-based model to preserve the... 

    Lightweight fuzzy extractor based on LPN for device and biometric authentication in IoT

    , Article IEEE Internet of Things Journal ; Volume 8, Issue 13 , 2021 , Pages 10706-10713 ; 23274662 (ISSN) Ebrahimi, S ; Bayat Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    User and device biometrics are proven to be a reliable source for authentication, especially for the Internet-of-Things (IoT) applications. One of the methods to employ biometric data in authentication are fuzzy extractors (FE) that can extract cryptographically secure and reproducible keys from noisy biometric sources with some entropy loss. It has been shown that one can reliably build an FE based on the learning parity with noise (LPN) problem with higher error-tolerance than previous FE schemes. However, the only available LPN-based FE implementation suffers from extreme resource demands that are not practical for IoT devices. This article proposes a lightweight hardware/software (HW/SW)... 

    High-throughput low-complexity unified multipliers over GF(2m) in dual and triangular bases

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume PP, Issue 99 , 2016 ; 15498328 (ISSN) Salarifard, R ; Bayat Sarmadi, S ; Farmani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    Abstract
    Multiplication is an essential operation in cryptographic computations. One of the important finite fields for such computations is the binary extension field. High-throughput low-complexity multiplication architectures lead to more efficient cryptosystems. In this paper, a high-throughput low-complexity unified multiplier for triangular and dual bases is presented, and is referred to as basic architecture. This multiplier enjoys slightly simpler and more regular structure due to use of the mentioned bases. Additionally, structurally improved architectures have been proposed, which have smaller time complexity than basic ones. This is achieved by the use of parallel processing method.... 

    Secure two-party computation using an efficient garbled circuit by reducing data transfer

    , Article 8th International Conference on Applications and Techniques in Information Security, ATIS 2017, 6 July 2017 through 7 July 2017 ; Volume 719 , 2017 , Pages 23-34 ; 18650929 (ISSN); 9789811054204 (ISBN) Yalame, M. H ; Farzam, M. H ; Bayat Sarmadi, S ; Sharif University of Technology
    Springer Verlag  2017
    Abstract
    Secure computation has obtained significant attention in the literature recently. Classic architectures usually use either the Garbled Circuit (GC) or the Goldreich-Micali-Wigderson (GMW) protocols. So far, to reduce the complexity of communications in these protocols, various methods have been proposed. The best known work in both methods reduces the communication up to almost 2k-bits (k is the symmetric security parameter) for each AND gate, and using XOR gate is free. In this paper, by combining GC and GMW, we propose a scheme in the semi-honest adversary model. This scheme requires an Oblivious Transfer (OT) and a 2-bit data transfer for each AND gate, keeping XOR gates free. The... 

    A low-latency and low-complexity point-multiplication in ECC

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 65, Issue 9 , 2018 , Pages 2869-2877 ; 15498328 (ISSN) Salarifard, R ; Bayat Sarmadi, S ; Mosanaei Boorani, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    Elliptic curve cryptography (ECC) has received attention, because it can achieve the same security level as other asymmetric methods while using a key with smaller length. Although ECC is more efficient compared with other asymmetric methods, the fast computation of ECC is always desirable. In this paper, a fixed-base comb point multiplication method has been used to perform regular point multiplication. In addition, two low-complexity (LC) and low-latency (LL) architectures for the regular point multiplication using fixed-base comb method have been proposed. The point multiplication architectures have been implemented using field-programmable gate array and application-specific integrated... 

    Post-quantum cryptoprocessors optimized for edge and resource-constrained devices in IoT

    , Article IEEE Internet of Things Journal ; Volume 6, Issue 3 , 2019 , Pages 5500-5507 ; 23274662 (ISSN) Ebrahimi, S ; Bayat Sarmadi, S ; Mosanaei Boorani, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    By exponential increase in applications of the Internet of Things (IoT), such as smart ecosystems or e-health, more security threats have been introduced. In order to resist known attacks for IoT networks, multiple security protocols must be established among nodes. Thus, IoT devices are required to execute various cryptographic operations, such as public key encryption/decryption. However, classic public key cryptosystems, such as Rivest-Shammir-Adlemon and elliptic curve cryptography are computationally more complex to be efficiently implemented on IoT devices and are vulnerable regarding quantum attacks. Therefore, after complete development of quantum computing, these cryptosystems will... 

    Low-latency double point multiplication architecture using differential addition chain over GF( 2 m)

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 66, Issue 4 , 2019 , Pages 1465-1473 ; 15498328 (ISSN) Shahroodi, T ; Bayat-Sarmadi, S ; Mosanaei-Boorani, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    During the past decade, elliptic curve cryptography (ECC) has been widely deployed in different scenarios as the main asymmetric cryptosystem due to its smaller key length and relatively higher speed compared with other asymmetric cryptosystems. The most critical operation in ECC computation is point multiplication. In some popular applications such as signature verification schemes, the double point multiplication can be exploited. In this paper, we propose an algorithm and its corresponding architecture to speed up the double point multiplication using a modified binary differential addition chain. The proposed method is highly parallelizable and has been implemented on Virtex-4, Virtex-5,... 

    Implementation of supersingular isogeny-based diffie-hellman and key encapsulation using an efficient scheduling

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 67, Issue 12 , 2020 , Pages 4895-4903 Farzam, M. H ; Bayat Sarmadi, S ; Mosanaei Boorani, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Isogeny-based cryptography is one of the promising post-quantum candidates mainly because of its smaller public key length. Due to its high computational cost, efficient implementations are significantly important. In this paper, we have proposed a high-speed FPGA implementation of the supersingular isogeny Diffie-Hellman (SIDH) and key encapsulation (SIKE). To this end, we have adapted the algorithm of finding optimal large-degree isogeny computation strategy for hardware implementations. Using this algorithm, hardware-suited strategies (HSSs) can be devised. We have also developed a tool to schedule field arithmetic operations efficiently using constraint programming. This tool enables... 

    Efficient hardware implementations of legendre symbol suitable for mpc applications

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; 2021 ; 15498328 (ISSN) Taheri, F ; Bayat Sarmadi, S ; Ebrahimi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture... 

    High-Speed post-quantum cryptoprocessor based on RISC-V architecture for IoT

    , Article IEEE Internet of Things Journal ; Volume 9, Issue 17 , 2022 , Pages 15839-15846 ; 23274662 (ISSN) Hadayeghparast, S ; Bayat Sarmadi, S ; Ebrahimi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    Public-key plays a significant role in today's communication over the network. However, current state-of-the-art public-key encryption (PKE) schemes are too complex to be efficiently employed in resource-constrained devices. Moreover, they are vulnerable to quantum attacks and soon will not have the required security. In the last decade, lattice-based cryptography has been a progenitor platform of the post-quantum cryptography (PQC) due to its lower complexity, which makes it more suitable for Internet of Things applications. In this article, we propose an efficient implementation of the binary learning with errors over ring (Ring-BinLWE) on the reduced instruction set computer-five (RISC-V)... 

    A study of timing side-channel attacks and countermeasures on javascript and webassembly

    , Article ISeCure ; Volume 14, Issue 1 , 2022 , Pages 27-46 ; 20082045 (ISSN) Mazaheri, M. E ; Bayat Sarmadi, S ; Taheri Ardakani, F ; Sharif University of Technology
    Iranian Society of Cryptology  2022
    Abstract
    Side-channel attacks are a group of powerful attacks in hardware security that exploit the deficiencies in the implementation of systems. Timing side-channel attacks are one of the main side-channel attack categories that use the time difference of running an operation in different states. Many powerful attacks can be classified into this type of attack, including cache attacks. The limitation of these attacks is the need to run the spy program on the victim’s system. Various studies have tried to overcome this limitation by implementing these attacks remotely on JavaScript and WebAssembly. This paper provides the first comprehensive evaluation of timing side-channel attacks on JavaScript... 

    Efficient hardware implementations of legendre symbol suitable for Mpc applications

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 69, Issue 3 , 2022 , Pages 1231-1239 ; 15498328 (ISSN) Taheri, F ; Bayat Sarmadi, S ; Ebrahimi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture... 

    RISC-HD: lightweight risc-v processor for efficient hyperdimensional computing inference

    , Article IEEE Internet of Things Journal ; Volume 9, Issue 23 , 2022 , Pages 24030-24037 ; 23274662 (ISSN) Taheri, F ; Bayat Sarmadi, S ; Hadayeghparast, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    Hyperdimensional (HD) computing is a lightweight machine learning method widely used in Internet of Things applications for classification tasks. Although many hardware accelerators are proposed to improve the performance of HD, they suffer from low flexibility that makes them not practical in most real-life scenarios. To improve the flexibility, an open-source instruction set architecture (ISA) called RISC-V has been employed and extended for a specific application such as machine learning. This article aims to improve the efficiency and flexibility of HD computing for resource-constrained applications. To this end, we extend a RISC-V core (RI5CY) for HD computing called RISC-HD. First, to... 

    Fault-resilient lightweight cryptographic block ciphers for secure embedded systems

    , Article IEEE Embedded Systems Letters ; Vol. 6, issue. 4 , 2014 , pp. 89-92 ; ISSN: 19430663 Mozaffari Kermani, M ; Tian, K ; Azarderakhsh, R ; Bayat Sarmadi, S ; Sharif University of Technology
    Abstract
    The development of extremely-constrained embedded systems having sensitive nodes such as RFID tags and nanosensors necessitates the use of lightweight block ciphers. Nevertheless, providing the required security properties does not guarantee their reliability and hardware assurance when the architectures are prone to natural and malicious faults. In this letter, error detection schemes for lightweight block ciphers are proposed with the case study of XTEA (eXtended TEA). Lightweight block ciphers such as XTEA, PRESENT, SIMON, and the like might be better suited for low-resource deeply-embedded systems compared to the Advanced Encryption Standard. Three different error detection approaches... 

    Reliable concurrent error detection architectures for extended euclidean-based division over (2m)

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Vol. 22, Issue. 5 , 2014 , pp. 995-1003 Mozaffari-Kermani, M ; Azarderakhsh, R ; Lee, C. Y ; Bayat-Sarmadi, S ; Sharif University of Technology
    Abstract
    The extended Euclidean algorithm (EEA) is an important scheme for performing the division operation in finite fields. Many sensitive and security-constrained applications such as those using the elliptic curve cryptography for establishing key agreement schemes, augmented encryption approaches, and digital signature algorithms utilize this operation in their structures. Although much study is performed to realize the EEA in hardware efficiently, research on its reliable implementations needs to be done to achieve fault-immune reliable structures. In this regard, this paper presents a new concurrent error detection (CED) scheme to provide reliability for the aforementioned sensitive and... 

    Systolic gaussian normal basis multiplier architectures suitable for high-performance applications

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 23, Issue 9 , 2015 , Pages 1969-1972 ; 10638210 (ISSN) Azarderakhsh, R ; Kermani, M. M ; Bayat Sarmadi, S ; Lee, C. Y ; Sharif University of Technology
    Abstract
    Normal basis multiplication in finite fields is vastly utilized in different applications, including error control coding and the like due to its advantageous characteristics and the fact that squaring of elements can be obtained without hardware complexity. In this brief, we present decomposition algorithms to develop novel systolic structures for digit-level Gaussian normal basis multiplication over GF (2m). The proposed architectures are suitable for high-performance applications, which require fast computations in finite fields with high throughputs. We also present the results of our application-specific integrated circuit synthesis using a 65-nm standard-cell library to benchmark the... 

    FPGA-based protection scheme against hardware trojan horse insertion using dummy logic

    , Article IEEE Embedded Systems Letters ; Volume 7, Issue 2 , 2015 , Pages 46-50 ; 19430663 (ISSN) Khaleghi, B ; Ahari, A ; Asadi, H ; Bayat-Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources with the proposed dummy logic. In the proposed scheme, we identify the unused resources at the device layout-level and offer dummy logic cells for different resources. The proposed HTH protection scheme has been applied on Xilinx Virtex devices implementing a set of IWLS benchmarks. The results show that by employing the proposed HTH...