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    An area and power optimization technique for CMOS bandgap voltage references

    , Article Analog Integrated Circuits and Signal Processing ; Volume 62, Issue 2 , 2010 , Pages 131-140 ; 09251030 (ISSN) Tajalli, A ; Chahardori, M ; Khodaverdi, A ; Sharif University of Technology
    2010
    Abstract
    This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in... 

    A new low voltage, high PSRR, CMOS bandgap voltage reference

    , Article 2008 IEEE International SOC Conference, SOCC, Newport Beach, CA, 17 September 2008 through 20 September 2008 ; 2008 , Pages 345-348 ; 9781424425969 (ISBN) Ashrafi, S. F ; Atarodi, M ; Chahardori, M ; Sharif University of Technology
    2008
    Abstract
    A new low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.18um CMOS technology, with a power supply of 1.4 volt. The results show PSRR is 65dB at 1MHz and the output voltage variation versus temperature (-40 to 140) is less than 0.1%. This circuit shows robustness against process variation. ©2008 IEEE