Sharif Digital Repository

In this paper, we consider resonant interaction between a surface wave and sub-harmonic interfacial waves forming a two-dimensional pattern at the interface between two fluid layers. The resulting interfacial pattern changes both in time and space. An image processing technique is proposed to extract information about the evolution of the component interfacial waves in a wave flume. The technique proved to give accurate and consistent results when applied to different stages of the interaction. The experimental measurements were used to verify the theoretical predictions. The method can be used for detection of some other wave motions  

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost effective protection against radiation effects in combinational logics, an accurate and fast method for identification of most susceptive gates and paths is needed. In this paper, an efficient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based... 

In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference... 

Login section is one of the most important parts of each system. This section is usually achieved through a username-password entering method. Since in these methods, user's security relays on how strong the password is, accordingly it is important how the password is provided. There are lots of different approaches in this regard which can be categorized in two main subgroups: Static and Dynamic passwords. Dynamic passwords are taking the lead in password generation context, since static password approaches suffer from some disadvantages like their vulnerability to easily get cracked, high possibility of oblivion and etc. In this paper, we introduce a novel dynamic password providing idea,... 

As technology size scales down toward lower two-digit nanometer dimensions, sensitivity of CMOS circuits to radiation effects increases. Static random access memory cells (SRAMs) that are mostly employed as high-performance and high-density memory cells are prone to radiation-induced single-event upsets. Therefore, designing reliable SRAM cells has always been a serious challenge. In this paper, we propose two novel SRAM cells, namely, RHD11 and RHD13, that provide more attractive features than their latest proposed counterparts. Simulation results show that our proposed SRAM cells as compared with some state-of-the-art designs have considerably higher robustness against single-event... 

This paper proposes and evaluates Low-overhead, Reliable Switch (LRS) architecture to enhance the reliability of Network-on-Chips (NoCs). The proposed switch architecture exploits information and hardware redundancies to eliminate retransmission of faulty flits. The LRS architecture creates a redundant copy of each newly received flit and stores the redundant flit in a duplicated flit buffer that is associated with the incoming channel of the flit. Flit buffers in the LRS are equipped with information redundancy to detect probable bit flip errors. When an error is detected in a flit buffer, its duplicated buffer is used to recover the correct value of the flit. In this way, the propagation... 

In this paper, a parallel algorithm is presented for data clustering on a multicomputer with star topology. This algorithm is fast and requires a small amount of memory per processing element, which makes it even suitable for SIMD implementation. The proposed parallel algorithm completes in O(K+S2-T2) steps for a clustering problem of N data patterns with M features per pattern and K clusters where S and T are the minimum numbers such that NM≤S! and KM≤T!, on the S-dimensional star graph  

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75%... 

time-optimal problem for redundantly actuated robots moving on a specified path is a challenging problem. Although the problem is well explored and there are proposed solutions based on phase plane analysis, there are still several unresolved issues regarding calculation of solution curves. In this paper, we explore the characteristics of the maximum velocity curve and propose an efficient algorithm to establish the solution curve. Then we propose a straightforward method to calculate the maximum or minimum possible acceleration on the path based on the pattern of saturated actuators, which substantially reduces the computational cost. Two numerical examples are provided to illustrate the... 

Motivated by recent laboratory and field observations, this paper reports the first quantitative measurements of the stabilization phase of interfacial instability in a two-layer fluid in surface wave motion. The instability results from the formation of a resonant triad between the surface wave and noise-level sub-harmonic interfacial waves. To exclude the effects of interfacial mixing on the interaction, the experiments were carried out with immiscible fluids. Carrying out a resonant interaction analysis to the third order of nonlinearity using a Lagrangian formulation, we also show for the first time that the three-wave resonance is inherently accompanied by a harmonic four-wave resonant... 

Recently, the trade-off between power consumption and fault tolerance in embedded processors has been highlighted. This paper proposes an approach to reduce dynamic power of conventional high-level fault-tolerant techniques used in the register file of processors, without affecting the effectiveness of the fault-tolerant techniques. The power reduction is based on the reduction of dynamic power of the unaccessed parts of the register file. This approach is applied to three transient fault-tolerant techniques: Single Error Correction (SEC) hamming code, duplication with parity, and Triple Modular Redundancy (TMR). As a case study, this approach is implemented on the register file of an... 

This paper proposes a new technique called CFEDC to detect and correct control flow errors (CFEs) without program interruption. The proposed technique is based on the modification of application software and minor changes in the underlying hardware. To demonstrate the effectiveness of CFEDC, it has been implemented on an OpenRISC 1200 as a case study. Analytical results for three workload programs show that this technique detects all CFEs and corrects on average about 81.6% of CFEs. These figures are achieved with zero error detection /correction latency. According to the experimental results, the overheads are generally low as compared to other techniques; the performance overhead and the... 

In this paper, a hierarchical routing protocol for wireless sensor networks is introduced that aims at reducing the energy imbalance among sensor nodes by integrating the distance of the nodes from the base station into clustering policies. Moreover, the proposed routing protocol does not need any centralized support from a certain node which is at odds with aiming to establish a scalable routing protocol. Mobility management is a salient feature of this protocol that guarantees reliable communications between mobile and static nodes. A simulator was developed in the MATLAB environment to evaluate the performance of this protocol. Simulations on two different network configurations are used... 

High reliability, high performance, low power consumption are the main objectives in the design of NoCs. These three design objectives are mostly conflicting and should be considered simultaneously in order to have an optimal design. This paper proposes a method based on duplicating the virtual channels of each NoC node as well as parity codes to prevent SEUs from producing erroneous data. The method is compared with two widely used SEU-tolerant methods i.e., the Switch to Switch and the End to End flow control methods, in terms of reliability, power consumption and performance. A flit level VHDL-based simulator and Synopsys Power Compiler tool have been used to extract experimental results.... 

High reliability, low power consumption and high performance are key objectives in the design of NoCs. These three design objectives should be considered simultaneously in order to have an optimal design. This paper proposes a method to reduce power consumption of an application specific NoC. This is done in two steps: 1) Extra virtual channels are used in the router architecture to increase the performance in an application specific NoC, and 2) The amount of the performance gain is then set to the initial point using frequency scaling technique, hence reducing the power consumption, without corruption of reliability. The simulation results show that the method can reduce the power... 

The phenomenon of the hydraulic jump is so complex that despite considerable laboratory and prototype studies, estimation of its main characteristics in a generalized and accurate form is still difficult. The Artificial Neural Network (ANN) approach aims at limiting the needs for costly and time-consuming experiments. In this study, two ANN models, multi-layer perceptron using back propagation algorithm (MLP/BP) and radial basis function using orthogonal least-squares algorithm (RBF/OLS), were used to predict the roller length, sequent depth, and the relative energy loss of the B-jump. Based on a pre-specified range of jump parameters, the input vectors include: upstream bed slope (tan θ),... 

This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental... 

In this paper, a hardware control flow checking technique is presented and evaluated. This technique uses reconfigurable of the shelf FPGA in order to concurrently check the execution flow of the target micro processor. The technique assigns signatures to the main program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. The main characteristic of this technique is its ability to be applied to any kind of processor architecture and platforms. The low imposed hardware and performance overhead by this technique makes it suitable for those applications in which cost is a major concern, such as... 

In this Paper, a software-based control flow checking technique called SWTES (Software-based error detection Technique using Encoded Signatures) is presented and evaluated. This technique is processor independent and can be applied to any kind of processors and microcontrollers. To implement this technique, the program is partitioned to a set of blocks and the encoded signatures are assigned during the compile time. In the run-time, the signatures are compared with the expected ones by a monitoring routine. The proposed technique is experimentally evaluated on an ATMEL MCS51 microcontroller using Software Implemented Fault Injection (SWIFI). The results show that this technique detects about...