Sharif Digital Repository

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are... 

Size and number of high-performance data centers are rapidly growing all around the world in recent years. The growth in the leakage power consumption of servers along with its exponential dependence on the ever increasing process variation in nanometer technologies has made it inevitable to move toward variation-aware power reduction strategies in data centers. In this paper, we address the problem of joint server placement and chassis consolidation to minimize power consumption of high-performance computing data centers under process variation. To this end, we introduce two variation-aware server placement heuristics as well as an integer linear programming (ILP)-based server placement... 

A wide range of scheduling algorithms used in the data centers have traditionally concentrated on enhancement of performance metrics. Recently, with the rapid growth of data centers in terms of both size and number, the power consumption has become a major challenge for both industry and society. At the software level, energy-aware task scheduling is an effective technique for power reduction in the data centers. However, most of the currently proposed energy-aware scheduling approaches are only paying attention to computation cost. In the other words, they ignore the energy consumed by the network equipment, namely communication cost. In this paper, the problem of scheduling... 

Corner-case analysis is a well-known technique to cope with occasional deviations occurring during the manufacturing process of semiconductors. However, the increasing amount of process variation in nanometer technologies has made it inevitable to move toward statistical analysis methods, instead of deterministic worst-case-based techniques, at all design levels. We show that by statically considering statistical effects of random and systematic process variation on performance and power consumption of a Multiprocessor System-on-Chip (MPSoC), significant power improvement can be achieved by static software-level optimizations such as task and communication scheduling. Moreover, we analyze... 

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

In recent years, Android is widely used in cell phones. Dalvik is the virtual machine which is embedded inside the Android operating system, and executes the Android-based applications. Thus, improving efficiency of the Dalvik virtual machine plays an important role in optimizing performance of android-based mobile phones. In this paper, we present a comprehensive analysis of the Dalvik bytecodes and their frequency of use in common Android applications and use the results to determine the most frequently used bytecodes in Dalvik virtual machine to identify best targets for improvement. Our analysis showed that over 82% of total execution time of our Android benchmarks is spent by only 5... 

Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical... 

The growth in number of data centers and its power consumption costs in recent years, along with ever increasing process variation in nanometer technologies emphasizes the need to incorporate variation-aware power reduction strategies in early design stages. Moreover, since the power characteristics of identically manufactured servers vary in the presence of process variation, their position in the data center should be optimally determined. In this paper, we introduce two heuristic variation-aware server placement algorithm based on power characteristic of servers and heat recirculation model of data center. In the next step, we utilize an Integer Linear Programming (ILP) based... 

Size and number of data centers are fast growing all over the world and their increasing total power consumption is a worldwide concern. Moreover, increase in the amount of process variation in nanometer technologies and its effect on total power consumption of servers has made it inevitable to move toward variation-aware power reduction strategies. This paper formulates a variation-aware joint server placement and task assignment method using Integer Linear Programming (ILP) to minimize total power consumption of data centers. We first determine the optimum placement of servers in the data center racks based on total power consumption of each server and the data center recirculation model... 

Latency-insensitive design (LID) is a correct by-construction methodology for system on chip design that prevents multiple iterations in synchronous system design. However, one problem in the LID is system throughput reduction. In this study, a protocol is proposed to increase the throughput of internal cores in the latency-insensitive systems when there are several repetitive structures. The validation of the protocol is checked for latency equivalency in various system graphs. A shell wrapper to implement the protocol is described and superimposed logic gates for the shell wrapper are formulated. Simulation is performed for 12 randomly generated systems and four actual systems. The... 

Communication wire delay between multiple blocks is becoming a critical issue in System on Chip (SoC) design. Scheduling-based Latency-Insensitive Design (LID) is a method to alleviate wire delays by utilizing a central scheduling scheme for periodic clock gating of the blocks. The scheduling scheme resides in shift registers as sequences of '1' and '0' bits. In many systems, these sequences are too long, and have large area overhead. This problem indisposes the implementation of the scheduling based protocol. This paper proposes an algorithm that finds sequences with shorter lengths in comparison with the prior algorithm. On synthetic/random test cases, the algorithm gives 45% reduction on... 

While performance and power consumption of processors present a classic trade-off in designing embedded hardware, software can be optimized in favor of both performance and energy. We evaluate the impact of optimizations at different stages of designing embedded software. We show that algorithm choice and compiler optimizations aimed at improving performance can also reduce energy consumption of an embedded processor. We also propose energy-aware compilation guidelines which can further reduce energy consumption without performance penalties. Our experimental results show that up to 85% energy reduction and 89% performance improvement can be achieved by these techniques  

In nanometer-scale process technologies, the effects of process variations are observed in Multiprocessor System-on-Chips (MPSoC) in terms of variations in frequencies and leakage powers among the processors on the same chip as well as across different chips of the same design. Traditionally, worst-case values are assumed for these parameters and then a deterministic optimization technique is applied to the MPSoC application under design. We show that such worst-case-based approaches are not optimal with the increasing variation observed at system-level, and instead, statistical approaches should be employed. We consider the problem of simultaneously choosing MPSoC architecture and task... 

Large scale Internet services are expected to only increase in complexity and popularity. Their energy consumption is also a major concern in data centers. Smart scheduling of their sub-services on data center Physical Machines (PM) can effectively improve their energy as well as performance. Since today servers are not energy-proportional yet, a major and traditionally neglected source of inefficiency in them is the utilization level of PMs. We present two scheduling algorithms for precedence-constrained parallel Virtual Machines (VM) in a virtualized data center where each VM represents a sub-service of the Internet-scale service. Our algorithms use virtualization technology to increase... 

The necessity and significance of improving the energy efficiency of cloud implementations have increased due to the rapid growth and proliferation of cloud computing services around the world. Virtual machines (VMs) comprise the backend of most, if not all, cloud computing services. Several VMs are often consolidated on a physical machine to efficiently utilize its resources. In this paper, we take into account the cooling and network structure of the datacenter host ing the physical machines when consolidating the VMs so that fewer racks and routers are employed, without compromising the service-level agreements; consequently, idle routing and cooling equipment can be turned off in order... 

Delay in communication wires causes design iterations in system-on-chip. Latency-insensitive design copes with this issue by encapsulating each core in a shell wrapper and inserting buffers in the wires to separate the design of core from that of communication wires. Scheduling-based latency-insensitive protocol is a methodology which employs shift registers for periodic clock gating of blocks instead of the shell wrappers. In many cases, the bit sequences inside the shift registers are too long and therefore consume a large area. This study presents a heuristic algorithm that optimises the bit sequences and produces them with shorter lengths compared with the existing method. The algorithm... 

Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm for MPSoCs. The proposed algorithm is able to maximize the total power yield of the chip under a given performance yield constraint by searching for the optimal task scheduling and power mode selection policy for a specified multiprocessor platform. Experimental results are gathered by... 

Parameter variations reveal themselves as different frequency and leakage powers per instances of the same MPSoC. By the increasing variation with technology scaling, worst-case-based scheduling algorithms result in either increasingly less optimal schedules or otherwise more lost yield. To address this problem, this paper introduces a variationaware task and communication scheduling algorithm for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to... 

Delay and leakage power uncertainty caused by process variation has become a challenging problem in deep submicron technologies. In recent years, the designers have developed methods to tackle this problem in many design levels such as high level synthesis and system level synthesis. This paper addresses the problem of variation-aware task scheduling and binding for multiprocessor system-on-chip (MPSoC). We consider both delay and leakage power variations during the process of finding the best schedule so that leakier processors are less utilized and can be more frequently put in sleep mode to reduce power. Our algorithm takes advantage of event tables to accelerate the statistical timing...