Sharif Digital Repository

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM in cache memories. However, STT-MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error-Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT-MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations... 

The emergence of mobile IoT applications in recent years and the challenge of routing in their infrastructures have motivated scholars to propose appropriate routing mechanisms for such systems. Meanwhile, the IPv6 Routing Protocol for Low Power and Lossy Networks (RPL) is the standard routing protocol for IoT infrastructures. Nevertheless, RPL was mainly designed to comply with the primitive requirements of static IoT applications and it behaves poorly in confronting with the severe alterations in mobile conditions. The most important factor for such a poor behavior in mobile applications is the inappropriate design of OFs, which determine RPL's routing policies in the network. Therefore,... 

A commercial gas-atomized aluminum powder was mechanically milled in a planetary ball mill under an argon atmosphere for 12 h to produce alumina dispersion strengthened aluminum powder. Transmission electron microscopy (TEM) revealed that about 2 vol.% alumina particles with an average size of 100 nm were distributed in the aluminum matrix. The nanocomposite powder was canned in an aluminum container, vacuum de-gassed, and hot extruded at 723 K at an extrusion ratio of 16:1. The creep behavior of the extruded billet in the direction of extrusion was examined at a constant applied load ranging from 10 to 40 MPa at temperatures of 648, 673 and 723 K. A threshold creep-stress was noticed which... 

Spin-transfer-torque RAMs (STT-RAMs) are the most promising technology for replacing Static RAMs (SRAMs) in on-chip caches. One of the major problems in STT-RAMs is the high error rate due to stochastic switching in write operations. Cache replacement algorithms have a major role in the number of write operations into the caches. Due to this fact, it is necessary to redesign cache replacement algorithms to consider the new challenges of STT-RAM caches. This paper proposes a cache replacement algorithm, which is called least error rate (LER) , to reduce the error rate in L2 caches. The main idea is to place the incoming block in a line that incurs the minimum error rate in write operation.... 

SRAM-based scratchpad memories (SPMs) used in embedded systems impose high leakage power. Designing SPMs based on non-volatile memories (NVMs) were proposed as NVMs have negligible leakage power. The main problem of utilizing NVMs across the SPM is their limited number of write cycles (endurance). This problem threatens the reliability of NVM-based SPMs. To alleviate the problem of limited endurance in NVM-based SPMs, this paper proposes a method, called overwrite purging through in-execution memory address snooping (OPTIMAS). The main idea behind the proposed method is to control the lifetime of NVM-based SPMs, directly by a hardware unit, outside of the SPM mapping algorithm. This idea... 

As the emergence of Internet of Things (IoT) brings the realization of ubiquitous connectivity ever closer, our reliance on these applications gets more important. Nowadays, such connected devices could be found everywhere, from home appliances to industrial control systems and environmental monitoring applications. One of the main challenges in IoT infrastructures is that of reliability, which emboldens itself in the context of Low-power and Lossy Networks (LLN) as they are inherently prone to packet loss as a result of their environmental and design constraints. Therefore, reliability of IoT devices becomes crucially important. With communication, the most important consideration in these... 

In this paper, a noise amplifier circuit in the L-band frequency (lGHz-2GHz) has been designed and implemented through the Advanced Design System (ADS) software. In this circuit, the Cascade technique is utilized in order to amplify the signal. In addition, current reuse, in-ductive feedback, and the inductive square pair techniques are exploited to increase the gain in linearity mode, isolate the signal, and match the input and output networks. There are three objectives for designing this circuit, i.e., increasing the gain, improving the signal stability in the Frequency linearity Bandwidth (L), and enhancement in the NF value. The proposed circuit includes four levels of transistors with... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAMseems to be themost promising alternative.With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches.High probability of write error due to stochastic switching is amajor problemin STT-RAMs. Conventional Error-CorrectingCodes (ECCs) impose significant area and energy consumption overheads to protect STT-RAMcaches. These overheads in multi-core processors with... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

Recently, energy harvesting systems that utilize hybrid NVM-SRAM memory in their designs are introduced as a promising alternative for battery-operated systems. Since the ambient input power of an energy harvesting system fluctuates as the environmental conditions change, the system may stop the execution of programs until it receives enough energy to continue the execution. Resuming the execution of a program after the suspension may lead to data inconsistency in an energy harvesting system and threatens the correct functionality of the programs. In this paper, we propose COACH, an energy-efficient consistency-aware memory scheme which guarantees the correct functionality and consistency of... 

Emerging STT-MRAM memories are promising alternatives for SRAM memories to tackle their low density and high static power consumption, but impose high energy consumption for reliable read/write operations. However, absolute data integrity is not required for many approximate computing applications, allowing energy savings with minimal quality loss. This paper proposes QuARK, a hardware/software approach for trading reliability of STT-MRAM caches for energy savings in the on-chip memory hierarchy of multi- A nd many-core systems running approximate applications. In contrast to SRAM-based cache-way-level actuators, QuARK utilizes fine-grained cache-line-level actuation knobs with different... 

Recently, IoT has been massively applied in different areas of human life. Meanwhile, in many of the IoT applications, e.g., the remote patient health-care monitoring systems, the reliability of communications, and the consumed energy in IoT devices, which are mostly battery-operated, are very challenging. Since IoT devices are typically operated in lossy environments, providing a reliable transmission for the packets imposes a noticeable amount of energy consumption. In addition, the runtime movement of the IoT devices in mobile networks further intensifies these issues. Therefore, the applied policies in the IPv6 RPL as the standard routing mechanism in IoT networks, play an important role... 

Damage tolerance improvement has been reported by laminating aluminum alloys and composites by researchers. Three-layer laminates comprising Al6061 outer layers and Al1050 interlayer have been roll bonded in this research. While most of the works done have focused on fracture properties of roll bonded Al laminates in crack arrester geometry, this study explores their behavior in crack divider configuration. Rolling strain is varied to control the interfacial bonding in laminates. The fracture behavior of laminates and the constituent material was examined via three-point bending and impact tests. This study presents significant improvement in damage tolerance of laminates compared to their... 

Tackling the dark silicon problem in a heterogeneous multi-core system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/realtime application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability-and deadline-aware mapping and scheduling algorithm for heterogeneous multi-core systems. READY utilizes an adaptive power constraint... 

Tackling the dark silicon problem in a heterogeneous multicore system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/real-time application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability-and deadline-aware mapping and scheduling algorithm for heterogeneous multicore systems. READY utilizes an adaptive power constraint... 

Reliability of routing mechanisms in wireless networks is typically measured with Packet Delivery Ratio (PDR). Basically, PDR is reported with an optimistic assumption that the topology is fully constructed, and the nodes have started their packet transmission. This is despite the fact that prior to being able to transmit packets, nodes must first join the network, and then try to keep connected as much as possible. This is a key factor in the overall reliability provided by the routing protocols, especially in mobile IoT applications, where disconnections occur frequently. Nevertheless, there is a lack of appropriate metrics, which could evaluate the routing mechanisms from this... 

Different architectures of layered laminates comprising two exterior layers of Al-Mg-Si/SiC metal matrix composite and an Al1050 ductile interlayer were fabricated by means of hot roll-bonding with applying different strains of εr = 39%, 51%, and 63%. For monolithics production, ceramic particulate reinforcement contents of 0, 5, 10, and 15 vol% were utilized. The aim of introducing ductile metal interlayer was to compensate the low toughness of composite layers and consequently enhancement of damage tolerance of bundled structures along with prevention of their catastrophic failure through activation of extrinsic toughening mechanism. Effects of architectural characteristics and fabrication...