Sharif Digital Repository

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM in cache memories. However, STT-MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error-Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT-MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations... 

The flexibility of software-based fault tolerant approaches in providing the required level of reliability Commer-cial-Off-The Shelf (COTS) devices made them the first choice in designing safety-critical systems. In this paper, we propose a reliability improvement method for COTS-based systems, so-called, RI-COTS. The main idea behind RI-COTS is to establish a tradeoff between reliability and performance of COTS system through controlling redundant execution at instruction level. RI-COTS is implemented on LEON2 processor VHDL model. Our simulation results show that comparing with the most related studies, RI-COTS can improve the fault detection capability by 20% with only 4% performance... 

Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, the reliability of STT-MRAMs is threatened by high probability of read disturbance and write failure. Both read disturbance and write failure, which cause a soft error in the cache cells, have an asymmetric behavior. Read disturbance occurs only in STT-MRAM cells storing '1' value, and write failure error rate in a → 1 transition is much higher than that in a 1 → 0 transition. In this paper, we propose Read/write Error-rate Aware Coding Technique (REACT) to improve the... 

Energy consumption is a major challenge in IoT devices, which was aimed to be improved by employing energy-efficient objective functions (OFs) in the structure of the RPL routing protocol. Meanwhile, the majority of the existing OFs mainly perform the parent selection based on the gathered information from the routing layer. Nevertheless, based on our investigations, there exists a series of transmission operations in the medium access control (MAC) layer, which significantly affects the energy consumption in IoT devices. Therefore, in this article, we propose ELITE, an energy-efficient cross-layer OF, which introduces a novel routing metric, called strobe per packet ratio (SPR). SPR... 

In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances and write failures are the major reliability problems in STTRAM caches. These disturbance/failure rates are directly affected not only by workload behaviors, but also by process variations. Several studies characterized the reliability of STTRAM caches just for one cell, but vulnerability of STT-RAM caches cannot be directly derived from these models. This paper extrapolates the reliability characteristics of one STTRAM cell presented in previous studies to the... 

Nowadays, leakage energy constitutes up to 80% of total cache energy consumption and tag array is responsible for a considerable fraction of static energy consumption. An approach to reduce static energy consumption is to replace SRAMs by STT-RAMs with near zero leakage power. However, a problem of an STT-RAM cell is its limited write endurance. In spite of previous studies which have targeted the data array, in this study STT-RAMs are used in the L1 tag array. To solve the write endurance problem, this paper proposes an STTRAM/SRAM tag architecture. Considering the spatial locality of memory references, the lower significant bitlines of the tag update more. The SRAM part handles the updates... 

Due to serious problems of SRAM-based caches in nano-scale technologies, researchers seek for new alternatives. Among the existing options, STT-RAMseems to be themost promising alternative.With high density and negligible leakage power, STT-RAMs open a new door to respond to future demands of multi-core systems, i.e., large on-chip caches. However, several problems in STT-RAMs should be overcome to make it applicable in on-chip caches.High probability of write error due to stochastic switching is amajor problemin STT-RAMs. Conventional Error-CorrectingCodes (ECCs) impose significant area and energy consumption overheads to protect STT-RAMcaches. These overheads in multi-core processors with... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

With the recent development in Non-Volatile Memory (NVM) technologies, several studies have suggested using them as an alternative to SRAMs in on-chip caches. However, limited endurance of NVMs is a major challenge when employed in the caches. This paper proposes a data manipulation technique, so-called Wearout Informed Pattern Elimination (WIPE), to improve the endurance of NVM-based caches by reducing the activity of frequent data patterns. Simulation results show that WIPE improves the endurance by up to 93% with negligible overheads. © 2017 IEEE  

With the widespread use of Internet of Things (IoT) in every aspect of human's daily life, communications of such an enormous amount of existing embedded devices in these systems arise many new challenges from power consumption, performance, and reliability perspectives. Communications in an IoT infrastructure are managed by a set of policies which are determined by Objective Functions (OFs). Thus, OFs are the most important contributors in facing with the mentioned challenges. In this paper, due to the lack of information on how OFs affect the primary properties of an IoT infrastructure, we have compared three well-known OFs (OF0, MRHOF, and OFFL) from power consumption, performance, and... 

Recent developments in Non-Volatile Memories (NVMs) have introduced them as an alternative for SRAMs in on-chip caches. Besides the promising features of NVMs, e.g., near-zero leakage power, immunity to radiation-induced particle strike, and higher density, a major drawback of NVM-based caches is their short lifetime due to limited write endurance. This paper first reveals that in L1 caches, the lifetime of data-cache (D-cache) is about 472x shorter than that of instruction-cache (I-cache) due to extreme imbalance write stress between the two. Then, we propose a technique, so-called Alternating Cache Allocation to Conduct Higher Endurance (A-CACHE), to improve the lifetime of... 

As the emergence of Internet of Things (IoT) brings the realization of ubiquitous connectivity ever closer, our reliance on these applications gets more important. Nowadays, such connected devices could be found everywhere, from home appliances to industrial control systems and environmental monitoring applications. One of the main challenges in IoT infrastructures is that of reliability, which emboldens itself in the context of Low-power and Lossy Networks (LLN) as they are inherently prone to packet loss as a result of their environmental and design constraints. Therefore, reliability of IoT devices becomes crucially important. With communication, the most important consideration in these... 

The emergence of mobile IoT applications in recent years and the challenge of routing in their infrastructures have motivated scholars to propose appropriate routing mechanisms for such systems. Meanwhile, the IPv6 Routing Protocol for Low Power and Lossy Networks (RPL) is the standard routing protocol for IoT infrastructures. Nevertheless, RPL was mainly designed to comply with the primitive requirements of static IoT applications and it behaves poorly in confronting with the severe alterations in mobile conditions. The most important factor for such a poor behavior in mobile applications is the inappropriate design of OFs, which determine RPL's routing policies in the network. Therefore,... 

Spin-Transfer Torque Random Access Memories (STT-RAMs) are a promising alternative to SRAMs in on-chip caches. STT-RAMs face with a high error rate in write operations due to stochastic switching. To alleviate this problem, Error-Correcting Codes (ECCs) are commonly used, which results in a significant area and energy consumption overhead. This paper proposes an efficient technique, so-called Adaptive Way Allocation for Reconfigurable ECCs (AWARE), to correct write errors in STT-RAM caches. AWARE exploits the asymmetric error rate in cell switching directions, which leads to data-dependent write error rates, to reduce the ECC overheads without compromising the reliability of the cache. To... 

In this paper, a noise amplifier circuit in the L-band frequency (lGHz-2GHz) has been designed and implemented through the Advanced Design System (ADS) software. In this circuit, the Cascade technique is utilized in order to amplify the signal. In addition, current reuse, in-ductive feedback, and the inductive square pair techniques are exploited to increase the gain in linearity mode, isolate the signal, and match the input and output networks. There are three objectives for designing this circuit, i.e., increasing the gain, improving the signal stability in the Frequency linearity Bandwidth (L), and enhancement in the NF value. The proposed circuit includes four levels of transistors with... 

Recently, energy harvesting systems that utilize hybrid NVM-SRAM memory in their designs are introduced as a promising alternative for battery-operated systems. Since the ambient input power of an energy harvesting system fluctuates as the environmental conditions change, the system may stop the execution of programs until it receives enough energy to continue the execution. Resuming the execution of a program after the suspension may lead to data inconsistency in an energy harvesting system and threatens the correct functionality of the programs. In this article, we propose COACH, an energy-efficient consistency-aware memory scheme which guarantees the correct functionality and consistency... 

Recently, energy harvesting systems that utilize hybrid NVM-SRAM memory in their designs are introduced as a promising alternative for battery-operated systems. Since the ambient input power of an energy harvesting system fluctuates as the environmental conditions change, the system may stop the execution of programs until it receives enough energy to continue the execution. Resuming the execution of a program after the suspension may lead to data inconsistency in an energy harvesting system and threatens the correct functionality of the programs. In this paper, we propose COACH, an energy-efficient consistency-aware memory scheme which guarantees the correct functionality and consistency of... 

Recently, energy harvesting systems that utilize hybrid NVM-SRAM memory in their designs are introduced as a promising alternative for battery-operated systems. Since the ambient input power of an energy harvesting system fluctuates as the environmental conditions change, the system may stop the execution of programs until it receives enough energy to continue the execution. Resuming the execution of a program after the suspension may lead to data inconsistency in an energy harvesting system and threatens the correct functionality of the programs. In this paper, we propose COACH, an energy-efficient consistency-aware memory scheme which guarantees the correct functionality and consistency of... 

Recently, IoT has been massively applied in different areas of human life. Meanwhile, in many of the IoT applications, e.g., the remote patient health-care monitoring systems, the reliability of communications, and the consumed energy in IoT devices, which are mostly battery-operated, are very challenging. Since IoT devices are typically operated in lossy environments, providing a reliable transmission for the packets imposes a noticeable amount of energy consumption. In addition, the runtime movement of the IoT devices in mobile networks further intensifies these issues. Therefore, the applied policies in the IPv6 RPL as the standard routing mechanism in IoT networks, play an important role... 

Tackling the dark silicon problem in a heterogeneous multi-core system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/realtime application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability-and deadline-aware mapping and scheduling algorithm for heterogeneous multi-core systems. READY utilizes an adaptive power constraint...