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    Low-power DAC with charge redistribution sampling method for SAR ADCs

    , Article Electronics Letters ; Volume 52, Issue 3 , 2016 , Pages 187-188 ; 00135194 (ISSN) Yazdani, B ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Institution of Engineering and Technology 
    Abstract
    A sampling and switching method for a binary weighted digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. This sampling method is proposed to reduce the switching energy. Thanks to the proposed switching method, only one reference voltage (Vcm = 1/2 Vref) is required which helps to improve the precision of the DAC along with energy reduction compared with those methods that use more than one reference voltage. The switching energy and area of the DAC reduce by 97.66% and 50% compared with the conventional binary weighted DAC  

    A wide dynamic range low power 2× time amplifier using current subtraction scheme

    , Article 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, 22 May 2016 through 25 May 2016 ; Volume 2016-July , 2016 , Pages 462-465 ; 02714310 (ISSN); 9781479953400 (ISBN) Molaei, H ; Khorami, A ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Abstract
    The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

    Low power DAC with single capacitor sampling method for SAR ADCs

    , Article Electronics Letters ; Volume 52, Issue 14 , 2016 , Pages 1209-1210 ; 00135194 (ISSN) Yazdani, B ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Institution of Engineering and Technology  2016
    Abstract
    An ultra-efficient switching method for successive approximation register ADCs is proposed. In this method, the input signals are sampled in a special fashion to reduce the switching energy. Owing to the sampling method, only one reference voltage (Vq=Vref/4) is required to implement the switching steps. Therefore, in addition to reduction in the switching energy (due to the lower supply voltage), the precision of the DAC is improved. The proposed method reduces the switching energy and area by 99.41 and 50%, respectively, compared with the conventional method. © 2016 The Institution of Engineering and Technology  

    Low-power bottom-plate sampling capacitor-splitting DAC for SAR ADCs

    , Article Electronics Letters ; Volume 52, Issue 11 , 2016 , Pages 913-915 ; 00135194 (ISSN) Yazdani, B ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Institution of Engineering and Technology  2016
    Abstract
    A highly energy-efficient switching method for capacitor-splitting digital-to-analogue converter (DAC) in successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. In the proposed DAC, a bottom-plate sampling method is introduced which requires only one reference voltage (Vcm = 1/2Vref) during the entire DAC switching steps. Therefore, in addition to the switching energy reduction, the precision of the DAC is increased since only one reference voltage is used. The DAC average switching energy and the area are reduced by 98.44% and 50% compared with the conventional binary weighted DAC  

    An accurate low-power DAC for SAR ADCs

    , Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) Yazdani, S. B ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    Abstract
    A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©... 

    Design of low power comparator-reduced hybrid ADC

    , Article Microelectronics Journal ; Volume 79 , 2018 , Pages 79-90 ; 00262692 (ISSN) Molaei, H ; Hajsadeghi, K ; Khorami, A ; Sharif University of Technology
    Elsevier Ltd  2018
    Abstract
    This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s... 

    Analysis of the effects of clock imperfections in N-path filters

    , Article Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, 7 June 2015 through 10 June 2015 ; June , 2015 , Page(s): 1 - 4 ; 9781479988938 (ISBN) Nikoofard, A ; Kananian, S ; Khorami, A ; Fotowat Ahmady, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    In this paper, the effect of imperfections on the behavior of N-path filters is investigated. Exact mathematical derivations are presented which describe the effect of clock skew and finite fall/rise time on the impedance transformation behavior of N-path filters. In the ideal case, the N-path filter is supposed to provide a short-circuit to the ground for undesired frequency contents and an open-circuit for the desired signal so that it lies within the passband of the filter. It is shown that clock skew and finite clock fall/rise time result in a non-zero impedance for frequency contents other than the clock frequency and a smaller impedance for the desired voltage. In a real circuit with... 

    A four bit low power 165MS/s flash-SAR ADC for sigma-delta ADC application

    , Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016-March , 2016 , Pages 153-156 ; 9781509002467 (ISBN) Molaei, H ; Khorami, A ; Eslampanah Sendi, M. S ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    Abstract
    A low power four bit mixed Successive Approximation Register (SAR)-Flash Analog to Digital Converter (ADC) for Sigma-Delta ADC applications is presented. The ADC uses three comparators in order to reduce the latency of typical SAR ADCs. Three comparators are used for conversion of 2 bits per one clock cycle. One of the Digital to Analog Converters (DACs) is replaced by three resistors which can save power and area. The ADC is simulated by Cadence Spectre using TSMC 0.18um COMS technology. The power consumption at 165MS/s and 1.8V supply voltage is 1.8mW. The SNDR and SFDR for 10MHz input are 19.8dB and 28.4dB, respectively  

    Solute dispersion by electroosmotic flow through soft microchannels

    , Article Sensors and Actuators, B: Chemical ; Volume 255, Part 3 , February , 2018 , Pages 3585-3600 ; 09254005 (ISSN) Hoshyargar, V ; Khorami, A ; Ashrafizadeh, S. N ; Sadeghi, A ; Sharif University of Technology
    Elsevier B.V  2018
    Abstract
    We study the hydrodynamic dispersion (HD) by electroosmotic flow in soft microchannels. Considering a fully developed flow in a slit microchannel of low surface potential and adopting the Taylor dispersion theory, we derive analytical solutions for the solute concentration field and the effective dispersion coefficient. We also conduct numerical analyses to broaden the paper's scope to high surface potentials and to specify a criterion for the validity of the Debye-Hückel linearization in soft microconduits as well as to investigate the broadening of an analyte band from the time of injection. It is demonstrated that the effective dispersion coefficient of a neutral solute band is generally...