Sharif Digital Repository

The rule based scheduling algorithms are a new trend in grid scheduling algorithms; the combination of rule based algorithms for resource selection with various dispatching rules for queuing of jobs can improve or deteriorate their performance. Thus, choosing a proper queuing strategy for each algorithm is a prominent issue in scheduling. In this paper, we introduce two new dispatching rules for resource selection and three new dispatching rules for queuing of jobs; we evaluate the performance of various combinations of these new rule based scheduling algorithms and queuing strategies. Also, we use some major combination of rule based scheduling algorithms with some important queuing... 

Grid scheduling problems are dynamic as the jobs and resources in the system vary overtime. The Rulebased scheduling algorithms are a new trend in grid scheduling which are applicable in dynamic grid environments; The arriving jobs waiting for execution is ordered according to a certain rule and they are dispatched for processing according to that order. Grid scheduling algorithms usually involve more than one objective function. In particular, it is not enough to minimize the Maximum completion time (Makespan) objective function without taking into consideration the lateness of the jobs (Tardiness). In this paper two novel dispatching rules are proposed that aims to minimize the maximum... 

Technology scaling increases clock rates and die sizes; therefore, power dissipation is predicted to soon become the key limiting factor on the performance of single-chip designs. NoC as an efficient and scalable on-chip communication architecture for SoC architectures, enables integration of a large number of computational and storage blocks on a single chip. Since different applications impose different traffic models to the network, in this paper we will analyze the power and energy consumption of the most popular traffic models, i.e., Uniform, Local, HotSpot and First Matrix Transpose, in two famous and well designed topologies, mesh and torus. We will also compare these topologies with... 

Asynchronous circuits have many advantages vs synchronous design styles like high performance and lower power consumption; however, there is a drawback of big overhead in handshake circuitry of these circuits. In this paper, we have reduced the amount of these extra circuits by take advantage of some compiler techniques. The compiler methods can be used innovatively to improve the synthesis results in terms of both power consumption and area, since these code motions lead to removing of completion detection and validity check parts of asynchronous designs. To the best of our knowledge this is the first effort in using the compiler pre-synthesis optimizations in asynchronous circuits to... 

There are two strategies for deadlock handling in routing algorithms in NoC: deadlock avoidance and deadlock recovery. Some deadlock recovery routing algorithms are re-injection based, such as: Compressionless (CR), Software-Based (SW-TFAR) and AFBAR. In spite of the performance comparison, none of existing researches have focused on the energy consumption of various routing algorithms. We evaluate these routing algorithms according to their energy consumption and latency. Our experimental results show the better performance and worse energy consumption of deadlock recovery routing algorithms compared to deadlock avoidance routing algorithms. In addition, the best and worst energy... 

In this paper we analyses the energy consumption of well known family of asynchronous circuits and present a new methodology for energy estimation of these circuits at intermediate-level of abstraction. Energy estimation is performed by simulating the intermediate format of the design. The number of Read and Write accesses on the ports of the concurrent processes are counted by analyzing the conditional and computational portion during the simulation which is the base of our estimation methodology. Our proposed power estimation scheme is faster than usual post-synthesis power estimation by an order of 9, while the estimated power resides in a boundary of 11% total imprecision. © 2007 IEEE  

Traffic models exert different message flows in a network and have a considerable effect on power consumption through different applications. So a good power analysis should consider traffic models. In this paper we present power and throughput models in terms of traffic rate parameters for the most popular traffic models, i.e. Uniform, Local, HotSpot and First Matrix Transpose (FMT) as a permutational traffic model. We also select Mesh topology as the most prominent NoC topology and validate the presented models by comparing our results against simulation results from Synopsys Power Compiler and Modelsim From the comparison, we show that our modeling approach leads to average error of 2%...