Sharif Digital Repository

In this paper, the systematic error due to interpolation in CMOS deep sub micron folding and interpolating ADC is studied and a closed form equation is presented to calculate the error as a function of interpolation coefficient, input voltage range and the number of input differential pairs. The amount of INL due to interpolation error can be considered as the lower bound for attainable INL of a specific ADC architecture. A case study for an 8_bit ADC is treated under consideration of different folding and interpolating factors. The trade off between power dissipation and ADC performance is characterized according to input stage characteristics. ©2006 IEEE  

An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE  

Direct discharge of high-strength industrial effluent often upsets municipal wastewater treatment plant processes. This pilot study was undertaken to evaluate the performance of a UASB system in pre-treating effluent from a medium-size traditional slaughterhouse. Experiments were conducted in a continuous flow 500-1 pilot plant initially inoculated with 200 1 municipal anaerobic digested sludge. With an influent COD concentration of 3000-5000 mg/l, the system was started with a loading of 1.8 kg COD/m3.d (F/M of 0.24 kg COD/kg VSS.d) at 25°C. The granules formed after 4 months of operation were dark brownish with a diameter of 1-4 mm and a settling velocity of 20 m/hr. Once granules were...