Sharif Digital Repository

FeVO4/CeO2 was applied in the electro-Fenton (EF) degradation of Methyl Orange (MO) as a model of wastewater pollution. The results of the characterization techniques indicate that FeVO4 with triclinic structure and face-centered cubic fluorite CeO2 maintained their structures during the nanocomposite synthesis. The effect of applied current intensity, initial pollutant concentration, initial pH, and catalyst weight was investigated. The MO removal reached 96.31% and chemical oxygen demand (COD) removal 70% for 60 min of the reaction. The presence of CeO2 in the nanocomposite plays a key role in H2O2 electro-generation as a significant factor in the electro-Fenton (EF) system. The metal... 

In this paper, we propose a new derivative-free preconditioned conjugate gradient method in order for solving large-scale square and under-determined nonlinear systems of equations. The proposed method is also equipped with a relaxed nonmonotone line search technique. Under some suitable assumptions, the global convergence property is established. Numerical results on some square and under-determined test systems show the efficiency and effectiveness of the new method in practice. An application of the new method for solving nonlinear integro-differential equations is also provided. © 2016 Elsevier Ltd  

Thermodynamic quantities such as proton affinity (PA) and molecular basicity (GB) for (CaO)n nanoclusters with n = 2–16 have been calculated using three computational models of the density functional theory (DFT) (Becke, 3-parameter, Lee-Yang-Parr (B3LYP), Minnesota 2006, Perdew-Wang 1991 (PW91), Coulomb attenuated method-B3LYP, and ωB97XD functionals); Møller-Plesset perturbation theory; and Hartree-Fock with the cc-PVNZ (n = D and T) basis set in the gas phase. Absolute deviation error (AAD%) indicates that obtained PA and GB values using DFT model and the B3LYP method with mean percentage errors of 0.77 and 0.90%, respectively, have the higher accuracy than the other methods and models.... 

Tackling the dark silicon problem in a heterogeneous multi-core system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/realtime application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability-and deadline-aware mapping and scheduling algorithm for heterogeneous multi-core systems. READY utilizes an adaptive power constraint... 

Tackling the dark silicon problem in a heterogeneous multicore system, the temperature constraints across the system should be addressed carefully by assigning a proper set of tasks to a pool of the heterogeneous cores during the run-time. When such a system is utilized in a reliable/real-time application, the reliability/timing constraints of the application should also be augmented to the temperature constraints and make the tasks mapping problem more and more complex. To solve the mapping problem in such a situation, we propose READY; an online reliability-and deadline-aware mapping and scheduling algorithm for heterogeneous multicore systems. READY utilizes an adaptive power constraint... 

Low power consumption, real-time computing, and high reliability are three key requirements/design objectives of real-time embedded systems. The standby-sparing technique can improve system reliability while it might increase the temperature of the system beyond safe limits. In this paper, we propose a thermal-aware standby-sparing (TASS) technique that aims at maximizing the Quality of Service (QoS) of soft real-time tasks, which is defined as a function of the finishing time of running tasks. The proposed technique tolerates permanent and transient faults for multicore real-time embedded systems while meeting the Thermal Safe Power (TSP) as the core-level power constraint, which avoids... 

Low power consumption, real-time computing, and high reliability are three key requirements/design objectives of real-time embedded systems. The standby-sparing technique can improve system reliability while it might increase the temperature of the system beyond safe limits. In this paper, we propose a thermal-aware standby-sparing (TASS) technique that aims at maximizing the Quality of Service (QoS) of soft real-time tasks, which is defined as a function of the finishing time of running tasks. The proposed technique tolerates permanent and transient faults for multicore real-time embedded systems while meeting the Thermal Safe Power (TSP) as the core-level power constraint, which avoids... 

Multicore platforms are becoming the dominant trend in designing Mixed-Criticality Systems (MCSs), which integrate applications of different levels of criticality into the same platform. A well-known MCS is the dual-criticality system that is composed of low-criticality and high-criticality tasks. The availability of multiple cores on a single chip provides opportunities to employ fault-Tolerant techniques, such as N-Modular Redundancy (NMR), to ensure the reliability of MCSs. However, applying fault-Tolerant techniques will increase the power consumption on the chip, and thereby on-chip temperatures might increase beyond safe limits. To prevent thermal emergencies, urgent countermeasures,... 

Increasing the number of cores integrated on a single chip offers a great potential for the implementation of fault-tolerant techniques to achieve high reliability in real-time embedded systems. Checkpointing with rollback-recovery is a well-established technique to tolerate transient faults in multicore platforms. To consider the worst-case fault occurrence scenario, checkpointing technique requires to re-execute some parts of the tasks, and that might lead to simultaneous execution of task parts with high power consumptions, which eventually might result in a peak power increase beyond the thermal design power (TDP). Exceeding TDP can elevate on-chip temperatures beyond safe limits, and...