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New approach to calculate energy on NoC
, Article 2008 International Conference on Computer and Communication Engineering, ICCCE08: Global Links for Human Development, Kuala Lumpur, 13 May 2008 through 15 May 2008 ; 2008 , Pages 1098-1104 ; 9781424416929 (ISBN) ; Nadi, M ; Rahmati, D ; Sharif University of Technology
2008
Abstract
Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in K-Ary n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results. ©2008 IEEE
An adaptive approach to manage the number of virtual channels
, Article 22nd International Conference on Advanced Information Networking and Applications Workshops/Symposia, AINA 2008, Gino-wan, Okinawa, 25 March 2008 through 28 March 2008 ; 2008 , Pages 353-358 ; 1550445X (ISSN) ; 0769530966 (ISBN); 9780769530963 (ISBN) ; Koohi, S ; Hessabi, S ; Rahmati, D ; Sharif University of Technology
2008
Abstract
Network-on-Chip (NoC) is a precious approach to handle huge number of transistors by virtue of technology scaling to lower than 50nm. Virtual channels have been introduced in order to improve the performance according to a timing multiplexing concept in each physical channel. The incremental effect of virtual channels on power consumption has been shown in literatures. The issue of power saving has always been controversial to many designers. In this paper, we introduce a new technique which tries to adaptively mange the number of virtual channels in order to reduce the power consumption while not degrading the performance of the network without any reconfiguration. Our experimental results...
A markovian performance model for networks-on-chip
, Article Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2008, 13 February 2008 through 15 February 2008, Toulouse ; 2008 , Pages 157-164 ; 0769530893 (ISBN); 9780769530895 (ISBN) ; Rahmati, D ; Sarbazi Azad, H ; Hessabi, S ; Sharif University of Technology
2008
Abstract
Network-on-Chip (NoC) has been proposed as a solution for addressing the design challenges of future high-performance nanoscale architectures. Thus, it is of crucial importance for a designer to ha ve access to fast methods for evaluating the performance of on-chip networks. To this end, we present a Markovian model for evaluating the latency and energy consumption of on-chip networks. We compute the a verage delay due to path contention, virtual channel and crossbar switch arbitration using a queuing-based approach, which can capture the blocking phenomena of wormhole switching quite accurately. The model is then used to estimate the power consumption of all routers in NoCs. The performance...
Effect of number of faults on NoC power and performance
, Article 13th International Conference on Parallel and Distributed Systems, ICPADS, Hsinchu, 5 December 2007 through 7 December 2007 ; Volume 1 , December , 2007 ; 15219097 (ISSN); 9781424418909 (ISBN) ; Nadi, M ; Manzuri Shalmani, M. T ; Rahmati, D ; Sharif University of Technology
2007
Abstract
According to International Technology Roadmap for Semiconductors (ITRS), before the end of this decade, we will be entering the era of a billion transistors on a single chip. The major threat toward the achievement of billion transistor on a chip is poor scalability of current interconnect infrastructure. With the advent of "Network on Chip (NoC)" various characters and methodologies of traditional networks were hardly considered on-chip. Failure, Power and Area are the major concepts that should be considered when migrating from traditional interconnection networks to NoCs. In this paper we study the effects of faulty links and nodes on power and performance of mesh based NoC, Also several...
Designing best effort networks-on-chip to meet hard latency constraints
, Article Transactions on Embedded Computing Systems ; Vol. 12, issue 4 , June , 2013 ; ISSN: 15399087 ; Rahmati, D ; Murali, S ; Sarbazi-Azad, H ; Benini, L ; Micheli, G. D ; Sharif University of Technology
Abstract
Many classes of applications require Quality of Service (QoS) guarantees from the system interconnect. In Networks-on-Chip (NoC) QoS guarantees usually translate into bandwidth and latency constraints for the traffic flows and require hardware support in the NoC fabric and its interfaces. In this article we present a novel NoC synthesis framework to automatically build networks that meet hard latency constraints of end-to-end traffic streams without requiring specialized hardware for the network components. The hard latency constraints are met by carefully designing the NoC topology and selecting the appropriate routes for flow using lean best-effort network components. We perform...