Sharif Digital Repository

In this paper, we introduce a notion of quantum discrepancy, a non-commutative version of combinatorial discrepancy which is defined for projection systems, i.e. finite sets of orthogonal projections, as non-commutative counterparts of set systems. We show that besides its natural algebraic formulation, quantum discrepancy, when restricted to set systems, has a probabilistic interpretation in terms of determinantal processes. Determinantal processes are a family of point processes with a rich algebraic structure. A common feature of this family is the local repulsive behavior of points. Alishahi and Zamani (2015) exploit this repelling property to construct low-discrepancy point... 

In this paper, sliding-mode control (SMC) is applied to a z-source converter to control output dc voltage of impedance network. The converter is assumed working in continuous conduction mode (CCM). First a comprehensive review of the literature for z-source inverter (ZSI) and use of sliding mode control in switched converters are performed. The procedure of SMC design used in ZSI is presented. The simulations for the application of SMC in z-source inverter are made and the results are illustrated. The results verify the effectiveness and robustness of the controller. © 2008 IEEE  

The aim of this study is to develop a non-linear robust controller with adaptive gains in order to prevent malaria epidemic as a positive system with an uncertain model. The malaria outbreak is modelled by seven non-linear coupled differential equations for the population variables: susceptible, exposed, symptomatic infected and recovered humans and the susceptible, exposed and infected mosquitoes. The non-linear robust adaptive integral-sliding-mode controller is developed in order to appropriately adjust the use of treated bednets, treatment rate of infected individuals and the use of insecticide spray to control malaria epidemic. Accordingly, the numbers of exposed and infected humans and... 

Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in... 

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write... 

As technology size scales down, magnetic tunnel junctions (MTJs) as a promising technology are becoming more and more sensitive to process variation, especially in oxide barrier thickness. Process variation particularly affects the cell resistance and the critical switching current for the smaller dimensions. This article proposes an MTJ cell with one free and two pinned layers, which highly improves the process variation robustness. By employing the spin transfer torque (STT)-spin-Hall effect (SHE) switching method, our proposed MTJ cell improves the switching speed and lowers the switching power consumption. Per simulations, an MRAM cell built with the proposed MTJ cell offers up to 36%... 

Fast and accurate estimation of soft error rate in VLSI circuits is an essential step in a soft error tolerant ASIC design. In order to have a cost effective protection against radiation effects in combinational logics, an accurate and fast method for identification of most susceptive gates and paths is needed. In this paper, an efficient, fast and accurate method for soft error propagation probability (SEPP) estimation is presented and its performance is evaluated. This method takes into account all three masking factors in multi cycles. It also considers multiple event transients as a new challenge in soft error tolerant VLSI circuit design. Compared with Monte Carlo (MC) simulation-based... 

In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but... 

In this paper, we propose two novel soft error tolerant latch circuits namely HRPU and HRUT. The proposed latches are both capable of fully tolerating single event upsets (SEUs). Also, they have the ability of enduring single event multiple upsets (SEMUs). Our simulation results show that, both of our HRPU and HRUT latches have higher robustness against SEMUs as compared with other recently proposed radiation hardened latches. We have also explored the effects of process and temperature variations on different design parameters such as delay and power consumption of our proposed latches and other leading SEU tolerant latches. Our simulation results also show that, compared with the reference... 

Demand for electricity, due to the fast growth in urbanization and industrialization, is on the rapid rise. Load shift is a basic method for demand side management (DSM) that can be used by the central controller in buildings and can lead to the maximum use of renewable energy sources, maximum economic benefits, and reduction of peak demand. This paper proposes an algorithm for shifting the flexible loads of four selected appliances with respect to boundary limits for each appliance. A standalone four-story building with different number of occupants is considered to evaluate this algorithm. The algorithm was trained on Richardson model to minimize two objectives including aggregated demand,... 

Mapping and Scheduling are two central and critical steps in design flow of the Networks on Chips (NoCs). They deal with implementation of the applications on NoCs. In this paper a novel energy aware algorithm, called EAMS, for mapping and scheduling of concurrent applications to NoC platforms is developed. It is considered that, the NoC architecture consists of a set of heterogeneous IP cores. The introduced algorithm finds a mapping of the tasks of the application to available IP cores so that the overall energy consumption, meeting task deadlines, is minimized