Sharif Digital Repository

As transistor dimensions continue to shrink, long-term reliability threats, such as Negative Bias Temperature Instability, affect multicore processors lifespan. This letter proposes a load balancing technique, based on the rate of integer and floating-point instructions per workloads. This technique classifies workloads into integer-majority and floating-point-majority classes and migrates workloads among cores in order to relax the stressed execution units. The context switching feature of operating system is employed to reduce implementation and performance overheads of the proposed technique. According to the simulations, the proposed technique reduces the aging rate of a multicore... 

Migration to Three Dimensional Integrated Circuits (3D ICs) can provide higher scalability, higher throughput, and lower power consumption with respect to Two Dimensional Integrated Circuits (2D ICs). Also, the latency bottleneck of interconnections in 2D ICs is efficiently solved in 3D ICs. This is due to the use of Through-Silicon-Vias (TSVs) in the communication structure of 3D ICs. TSVs are among the efficient fabrication mechanisms that connect stacked layers in 3D ICs. However, proximity and large size of TSVs make them highly prone to crosstalk faults. Crosstalk faults can cause mutual undesired influences between TSVs and thus seriously threat the reliability of data transfer on... 

Bias temperature instability (BTI) is known as one serious reliability concern in nanoscale technologies. BTI gradually increases the absolute value of threshold voltage (Vth) of MOS transistors. The main consequence of Vth shift of the SRAM cell transistors is the static noise margin (SNM) degradation. The SNM degradation of SRAM cells results in bit-flip occurrences due to transient faults and should be monitored accurately. This paper proposes a sensor called write current-based BTI sensor (WCBS) to assess the BTI-aging state of SRAM cells. The WCBS measures BTI-induced SNM degradation of SRAM cells by monitoring the maximum write current shifts due to BTI. The observations show that the... 

3D Network-on-Chips (3D NoCs) have higher scalability, higher throughput, and lower power consumption over 2D NoCs. However, the reliability of data transfer in 3D NoCs is seriously threatened by thermal problems. This is due to poor heat dissipation, inappropriate traffic distribution, and cooling restriction for layers away of the chip heat-sink in 3D NoCs. To solve this problem, this paper proposes an efficient deadlock-free and traffic-And thermal-Aware routing algorithm, called Floating XY-YX. The main idea behind Floating XY-YX routing algorithm is twofold: 1) to use XY and YX routing algorithms in consecutive layers in dessicate form, and 2) to evenly load the traffic, which is... 

Technology scaling has exacerbated the aging impact on the performance and reliability of integrated circuits. By entering into nanotechnology era in recent years, the power density per unit of area has increased, which leads to a higher chip temperature. Aging in a chip is originated from multiple phenomena; all of them are intensified by increased temperature. Several circuit- and architecture-level schemes tried to mitigate the aging in the literature. However, these schemes are not sufficient for multi-core systems due to their unawareness of the unique constraints and features of these platforms. In this paper, we propose a system-level aging mitigation method, so-called Adaptive Task... 

Technology scaling has exacerbated the aging impact on the performance and reliability of integrated circuits. By entering into nanotechnology era in recent years, the power density per unit of area has increased, which leads to a higher chip temperature. Aging in a chip is originated from multiple phenomena; all of them are intensified by increased temperature. Several circuit- and architecture-level schemes tried to mitigate the aging in the literature. However, these schemes are not sufficient for multi-core systems due to their unawareness of the unique constraints and features of these platforms. In this paper, we propose a system-level aging mitigation method, so-called Adaptive Task... 

Although many Dynamic Thermal Management (DTM) techniques are employed to overcome thermal problems in 3D NoCs, none of them consider temperature information of all nodes of a layer at the same time, so that they cannot reduce the temperature of the network properly.To overcome this problem, this paper proposes an efficient proactive thermal-aware routing algorithm, called Less Entrance to Hot Regions (LETHOR), to keep the NoC temperature lower than a predefined thermal limit. LETHOR routes the network packets based on the temperature information of all nodes in the layers instead of considering only the neighbor nodes in each hop. To this aim, LETHOR introduces a Hot Region in each layer... 

Embedded Systems (ESs) have migrated from special-purpose hardware to commodity hardware. These systems have also tended to Mixed-Criticality (MC) implementations, executing applications of different criticalities upon a shared platform. Multi-cores, which are commonly used to design MC Systems (MCSs), bring out new challenges due to the Process Variation (PV). Power and frequency asymmetry affects the predictability of ESs. In this work, variation-aware techniques are explored to not only improve the reliability of MCSs, but also aid the scheduling and energy saving of them. We leverage the Core-to-Core (C2C) variations to protect high-criticality tasks and provide full service for a high... 

Negative Bias Temperature Instability (NBTI) in CMOS devices is known as the major source of aging effect which is leading to performance and reliability degradation in modern processors. Instruction-cache (I-cache), which has a decisive role in performance and reliability of the processor, is one of the most prone modules to NBTI. Variations in duty cycle and long-time residency of data blocks in I-cache lines (stress condition) are the two major causes of NBTI acceleration. This paper proposes a novel I-cache management technique to minimize the aging effect in the I-cache SRAM cells. The proposed technique consists of a smart controller that monitors the cache lines behavior and... 

Wireless Sensor Networks (WSNs) are prone to faults due to battery depletion of nodes. A node failure can disturb routing as it plays a key role in transferring sensed data to the end users. This paper presents a Fault-Tolerant and Energy-Aware Mechanism (FTEAM), which prolongs the lifetime of WSNs. This mechanism can be applied to cluster-based WSN protocols. The main idea behind the FTEAM is to identify overlapped nodes and configure the most powerful ones to the sleep mode to save their energy for the purpose of replacing a failed Cluster Head (CH) with them. FTEAM not only provides fault tolerant sensor nodes, but also tackles the problem of emerging dead area in the network. Our... 

Embedded systems have migrated from special-purpose hardware to commodity hardware. These systems have also tended to Mixed-Criticality (MC) implementations, executing applications of different criticalities upon a shared platform. Multi-core processors, which are commonly used to design MC systems, bring out new challenges due to the process variations. Power and frequency asymmetry affects the predictability of embedded systems. In this work, variation-aware techniques are explored to not only improve the reliability of MC systems, but also aid the scheduling and energy saving of them. We leverage the core-to-core (C2C) variations to protect high-criticality tasks and provide full service... 

It is shown that a compact MOSFET-aging model for circuit simulation is possible by considering the dynamic trap-density increase, which is induced during circuit operation. The dynamic trap/detrap phenomenon, which influences the switching performance, is also considered on the basis of well-known previous results. Stress-dependent hot-carrier effect and NBTI effect, origins of the device aging, are modeled during the circuit simulation for each device by integrating the substrate current as well as by determining the oxide-field change due to the trapped carriers over the individual stress-duration periods. A self-consistent solution can be obtained only by iteratively solving the Poisson... 

We have developed a methodology to simulate circuit aging including the device fabrication variation with less simulation effort. As an example a 6T SRAM cell has been investigated. It is demonstrated that the variability range of the circuit performance is further enhanced due to the long-term device aging. Among the device parameters, the impurity concentration variation plays a particularly important role for the circuit performance variation. However, most sensitive for the aging degradation is the channel-length variation, because it increases the aging effect drastically. Further, the individual aging of each MOSFET is strongly dependent on the actual stress during circuit operation. ©... 

Low power consumption and high-reliability are often major objectives in the design of embedded systems. To reduce power consumption, embedded systems usually employ system-level power management techniques, e.g. Dynamic Voltage Scaling (DVS) and Dynamic Power Management (DPM). To achieve high reliability, embedded systems often exploit fault-tolerant techniques. Fault-tolerant techniques are in a trade-off with energy consumption, peak-power consumption, and temperature. Thus, different methods have been introduced that simultaneously consider reliability and power consumption as the system constraints. Several novel methods have been proposed in previous works to reduce the power... 

A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET modeling. The aging model considers the dynamic trap-density increase as a function of circuit-operation time with dynamically varying stress conditions for each individual MOSFET. A self-consistent solution is obtained by iteratively solving the Poisson equation including the trap density. The...