Sharif Digital Repository

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes.... 

In this paper, an analytic model of the energy consumption of the Stepwise Adiabatic Circuits (SAC) when it is possible to discharge the load capacitor is proposed. Using this model, analytical derivations are calculated which shows us the power saving of the SACs. Using analytical derivations, the sizing of a capacitor tank is determined for a desired energy saving. For example, the derivations predict that if the sizing of the 3-step series tank capacitors is equal to the load capacitor, the power saving is 55%. Also, if the sizing of the tank is very large the energy saving of a 3-step stepwise charging is equal to 66.7%. Several Simulations in 0.18μm CMOS technology prove the accuracy of... 

A charge sharing technique for high-speed double-tail comparators is presented. This technique is applied to the pre-amplifier stage of the dynamic comparators so that the maximum differential gain is applied to the latch during the latching process reducing the input referred offset voltage. In dynamic comparators a large portion of the input referred offset voltage is coming from the latch, and the proposed technique is introduced to alleviate this issue. Monte- Carlo simulations show that the proposed technique reduces the offset voltage from 16 mV to 8 mV. Due to the charge sharing technique, the pre-amplifier draws just enough power for its operation reducing the average power by 40%... 

The fast growth of battery-operated portable applications has compelled the static random access memory (SRAM) designers to consider sub-threshold operation as a viable choice to reduce the power consumption. To increase the hold, read and write static noise margin (SNM) in the sub-threshold regime many structures has been proposed adding extra transistors to the conventional 6T-cell. In this paper we propose a new 8T-cell SRAM that shows 90% improvement in read SNM while write and hold SNM reduction can be ignored (this negligible reduction is due to the two stack transistors in the proposed 8T-cell). Benefiting differential output voltage in the read operation, sense amplifier design is... 

The fast growth of battery operated devices has made low power SRAM designs a necessity in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The SRAM performance is limited by the cell stability during different operation. By adding extra transistor to the conventional 6T-cell, hold, read and write static noise margin (SNM) can be improved in the sub-threshold SRAM. In this paper we proposed a new 9T-cell SRAM that shows 80% and 50% improvement in read and write SNM respectively in comparison to the conventional 6T-cell SRAM. Using stack transistors in the leakage current path, the new structure shows lower bitline leakage assisting the sense... 

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. © 2019 Elsevier B.V  

In double tail comparators, the pre-amplifier amplifies the input differential voltage and when the output Vcm of the pre-amplifier becomes larger than Vth of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the pre-amplification delay is fixed to a value and cannot be set at the minimum required delay, to save power and improve offset. In fact, when the latch is activated the pre-amplifier output differential voltage is still growing but the latch finishes the comparison before the maximum differential gain is formed and applied to the latch. In this paper, a comparator is proposed in which the preamplifier is turned off when the maximum gain is...