Sharif Digital Repository

A novel method of transmitter (TX) leakage cancellation is presented to improve the dynamic range of the receiver for wideband code division multiple access applications. The large TX leakage is attenuated within the low noise amplifier (LNA) output using a feed-forward path without any LNA noise figure degradation. A prototype has been designed and laid out in 0.18 μm CMOS technology. It achieves a maximum TX rejection of 18.5 dB with only 5.2 mA current consumption from 1.8 V supply voltage. LNA P-1dBCP (1 dB gain compression point) against TX leakage improves by more than 10 dB. Post layout simulations verify these results. Proposed structure dispels the requirement of off-chip surface... 

An ultra-low power frequency-shift keying (FSK) demodulator based on injection-locking ring oscillator for wireless body area networks is presented. The proposed system uses the power-efficient injectionlocking ring oscillator (ILRO) to replace the LC oscillator which occupies much more area on chip with higher power consumption. In addition, through the ILRO, the frequency modulated input signal is converted to a full swing rectangular signal, which can be directly demodulated by a chain of down-conversion passive mixers, lowpass filters and a comparator. Power efficiency and simplicity of the proposed structure eliminate conventional FSK demodulator based on power-hungry phase locked... 

This article presents an applicable intuitive current-voltage model for long-channel transistors based on 2-D materials. This model carefully predicts the transistor behavior in the saturation and triode regions, which are important for analog and digital applications. Moreover, the effect of mobility degradation on the characteristics of the transistor is probed. As a case study, the developed model has been applied to a transistor with mono-layer MoS2 as the channel material. The excellent agreement with experimental data verifies the accuracy of the model. Finally, the introduced model has been utilized to design an amplifier, a differential pair, and a low-frequency common source mixer... 

In modern wireless near-filed power and data telemetry systems such as Implantable Medical Devices (IMD), a data rate of several Mbps is required, while the power carrier frequency is limited to few MHz. Therefore, bit rate is comparable to carrier frequency, and the modulated power carrier signal has amplitude, frequency, or phase variation in every cycle. In this paper a very fast amplitude shift keying (ASK) demodulator circuit is presented. The proposed demodulator is able to demodulate a cycle by cycle ASK modulated signal, and a data-rate-to-carrier (DRC) ratio of 100% is achievable. The circuit extracts the clock by limiting the incoming ASK signal. Cycle by cycle demodulation is done... 

In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively  

A novel frequency synthesizer architecture for reducing spur level is presented. By using a feedforward path a new zero in the transfer function is generated which enables us to increase the capacitor tied to the control voltage line and thus reducing spur level. A fast settling technique is also used to compensate the effect of spur reduction technique on settling time. Different blocks of frequency synthesizer are implemented in MATLAB/Simulink. Simulations show 13 dB improvement in reference spur level compared to conventional architecture for a 2.4 GHz frequency synthesizer  

In this paper, a low power receiver for medical implant communication service (MICS) is presented. Low power design is vital in the MICS applications since the implanted chip has to work for a long time without the need to change its battery. As a result, a merged N-path low noise amplifier (LNA) and mixer block is proposed. In this structure, the LNA and down-conversion mixer share a transconductance to lower the overall power consumption. An N-path feedback is utilized around the shared transconductance not only to improve the LNA selectivity and relax the linearity requirements but also to downconvert the radio frequency (RF) component and create the intermediate frequency (IF) signal. In... 

In this paper a 6-bit vector-sum phase shifter with a full 360° variable phase-shift range for S-band has been designed and simulated using standard 180 nm CMOS technology. A new In-phase and Quadrature (I and Q) network to generate quadrature signals with minimum I and Q amplitude mismatch over wide bandwidth is proposed and deployed in the vector sum phase shifter. The designed phase shifter achieves an RMS (root mean square) phase error less than 1.34° and an RMS amplitude error less than 0.43 dB over wide bandwidth of 2 – 4 GHz, resulting in a 6-bit resolution. The gain of phase shifter chain varies from 3 to −6 dB over S-band of 2 – 4 GHz. Moreover the input of phase shifter is widely... 

In this paper, a wideband full-360o phase shifter with 6 bits of accuracy has been designed and simulated with minimal root mean square (RMS) phase error. The proposed phase shifter deployed a feed forward path including a frequency-to-voltage converter (FVC) to minimize the mismatch in quadrature generation to eventually reduce the RMS phase error for S-band (2-4GHz) applications. The designed phase shifter in 180nm CMOS technology achieves an RMS phase error in the range of 0.607-1.18? with -50dBm input signal over 2-4GHz frequency band. With lower input signal of -75dBm, the RMS phase error is 0.621-1.34? for 2-4GHz input frequency. The proposed phase shifter shows an RMS amplitude error... 

This paper presents a cycle by cycle Frequency Shift Keying (FSK) demodulator, able to demodulate a FSK signal with 1% frequency modulation index (MI), in a single cycle. Based on the proposed demodulation scheme, a high rate data transmission link can be established through a high-Q inductive coupling link, breaking the basic tradeoff between the power transfer efficiency (PTE) and data rate in single carrier wireless power and data transfer systems. Designed and simulated with 0.18μ m CMOS process, the proposed FSK demodulator, detects successfully a 5Mbps data with a carrier frequency of 5MHz. A test chip is fabricated in 180nm CMOS technology. Measurement results shows that the... 

The Class-E power amplifier has been widely studied and formulated in the literature. Although the majority of reported inductive coupling wireless power transfer (WPT) systems use a class-E power amplifier for driving the primary coil, still there is a lack of a comprehensive study on class-E circuit dedicated to WPT, providing a set of closed form design equations for proper class-E operation. This paper presents the required design equations needed to design a 'true' class-E circuit for WPT applications. Equations for the series-tuned secondary coil WPT system are presented, as well as two different design procedures for the parallel-tuned secondary coil. The derived equations have been... 

In this paper a new low-voltage two-stage class-AB line driver for ADSL applications is presented. The new proposed line-driver consists of only two stages with a new method to control the quiescent current of the output stage. The low-voltage full-CMOS high-linear line driver shows -77 dB THD for a load as low as 20 ohms. The line driver has variable gain, attenuating the input signal from 0dB to -14dB with 2dB steps. The peak to peak differential output swing is 4.2-V from a 2.5-V Supply voltage in a 0.25um standard CMOS technology  

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called "Slew Boost" is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10bit 150MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp using 0.18um CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than 1mW from a single supply of 1 volt  

A 12 bit 25 MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 μm CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve requirements of 12 bit resolution and settling in 20 ns within 0.05% accuracy. However, pipeline ADCs are tolerant to comparator's offset, but using dynamic comparators, power dissipation can be reduced. So a dynamic comparator is designed which is more power efficient. Total power dissipation is about 76 mW from a single 3 V supply, where INL and DNL are 0.8 LSB and 0.6 LSB respectively. A SNDR of 70.1 dB is achieved. © 2003 IEEE  

An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called 'Slew Boost' is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10 bit 150 MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp, using 0.18 μm CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than I mW from a single supply of I volt. © 2003 ACM