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    Influence of photoanode architecture on light scattering mechanism and device performance of dye-sensitized solar cells using TiO2 hollow cubes and nanoparticles

    , Article Journal of the Taiwan Institute of Chemical Engineers ; Volume 86 , May , 2018 , Pages 81-91 ; 18761070 (ISSN) Sarvari, N ; Mohammadi, M. R ; Sharif University of Technology
    Taiwan Institute of Chemical Engineers  2018
    Abstract
    Herein, we report the impact of light scattering mechanism on photovoltaic and photoelectrochemical performance of dye-sensitized solar cell (DSC) devices composed of TiO2 nanoparticles and hollow cubes. DSCs are designed by two different light scattering modes (i.e., mode I in form of single layer electrode containing nanoparticles and hollow cubes and mode II in the form of double layer electrode comprising active and scattering layers made of nanoparticles and mixtures of nanoparticles and hollow cubes, respectively). The synthesized anatase-TiO2 hollow cubes (200–400 nm) and nanoparticles (15–30 nm) are employed to enhance the optical length and light harvesting of photoanodes,... 

    Enhanced electron collection efficiency of nanostructured dye-sensitized solar cells by incorporating TiO2 cubes

    , Article Journal of the American Ceramic Society ; Volume 101, Issue 1 , 2018 , Pages 293-306 ; 00027820 (ISSN) Sarvari, N ; Mohammadi, M. R ; Sharif University of Technology
    Blackwell Publishing Inc  2018
    Abstract
    Herein, enhancement of dye-sensitized solar cell (DSC) performance is reported by combining the merits of the dye loading of TiO2 nanoparticles and light scattering, straight carrier transport path, and efficient electron collection efficiency of TiO2 cubes. We fabricate DSC devices with various arrangement styles and compositions of the electrodes in the forms of monolayer and double layer films. For this purpose, the solvothermal synthesized TiO2 cubic particles (100-600 nm) are employed as the scattering layer, whereas TiO2 nanoparticles (15-30 nm) synthesized via a combination of solvothermal and sol-gel routes are used as the active layer of devices. We improve the photovoltaic... 

    A new method for the analysis of transmission property in carbon nanotubes using Green's function

    , Article Applied Physics A: Materials Science and Processing ; Volume 102, Issue 1 , 2011 , Pages 231-238 ; 09478396 (ISSN) Fathi, D ; Forouzandeh, B ; Sarvari, R ; Sharif University of Technology
    2011
    Abstract
    A new method for the analysis of electron transmission property in single-walled carbon nanotubes (SWCNTs) using Green's function is presented in this paper for the first time. Using the proposed method, a new relation for the transmission function through a deformed SWCNT is obtained, which depends on the energy variations and the coupling matrices related to the mechanical deformations applied to the structure of CNT. The obtained new relation is explained by the presented results in the literature  

    Power delivery solutions in 3-D processor-DRAM systems in presence of hot spots

    , Article 2014 IEEE 23rd Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2014, 26 October 2014 through 29 October 2014 ; Oct , 2014 , Pages 207-210 ; 9781479936410 (ISBN) Zabihi, M ; Radfar, F ; Sarvari, R ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2014
    Abstract
    An important application of 3-D integration technology is stacked processor-DRAM systems. One of the major design issues in 3-D processor-DRAM stacks is power delivery. Presence of hot spots, high density power regions, in processor die poses serious challenges to the design of power distribution network (PDN). In this paper, we investigate solutions to ensure power integrity in the hot spot regions  

    Comparison between optimal interconnection network in different 2D and 3D NoC structures

    , Article International System on Chip Conference ; 2014 , p. 171-176 Radfar, F ; Zabihi, M ; Sarvari, R ; Sharif University of Technology
    2014
    Abstract
    The current article studies optimal intercore interconnect network in a NoC structure for 2D and 3D mesh, torus and hypercube topologies. Optimal wire width/spacing is calculated by numerically maximizing bandwidth times the reciprocal delay, which depends on the technology node and hop length. Through 3D integration and increasing tiers, optimal interconnect width and spacing in torus and hypercube topologies will decrease. The core-to-core channel width in all topologies will be obtained by assigning 20% of the power consumption to the routers. By increasing number of cores, channel width will decrease due to reduced power consumption of each core. This is more in hypercube topology, due... 

    Investigation of quantum conductance in semiconductor single-wall carbon nanotubes: Effect of strain and impurity

    , Article Journal of Applied Physics ; Volume 110, Issue 6 , 2011 ; 00218979 (ISSN) Rabiee Golgir, H ; Faez, R ; Pazoki, M ; Karamitaheri, H ; Sarvari, R ; Sharif University of Technology
    2011
    Abstract
    In this paper the effect of strain and impurity on the quantum conductance of semiconducting carbon nanotubes (CNTs) have been studied by ab-initio calculations. The effect of strain and impurity on the CNT conducting behavior and physical characteristics, like density of states (DOS), band structure, and atomic local density of state (LDOS), is considered and discussed separately and simultaneously. Our results show that the quantum conductance of semiconductor CNTs is increased by compression strain, elongation strain, and replacing nitrogen and boron doping in its structure. The amount of increasing in the conductance depends on the type of strain and impurity. Conductance of CNT can be... 

    New approach to VLSI buffer modeling, considering overshooting effect

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 21, Issue 8 , August , 2013 , Pages 1568-1572 ; 10638210 (ISSN) Mehri, M ; Kouhani, M. H. M ; Masoumi, N ; Sarvari, R ; Sharif University of Technology
    2013
    Abstract
    In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis... 

    Impact of Temperature on Efficiency of CNT and Copper Interconnects

    , M.Sc. Thesis Sharif University of Technology (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    While digital IC technology scales down, the impact of size effects in copper interconnects become more important because wire dimensions reach the same order of electron mean free path yielding increased resistivity of metal due to surface and grain boundary scatterings. Hence, because of their longer MFP, Carbon nanotubes are proposed as potential candidates for replacing copper interconnects. Furthermore, wires, especially power and ground lines, are becoming more and more vulnerable to electromigration because of rapid grows in current densities which increases the temperature of IC and interconnects as well. Sub-ambient cooling has long been suggested for improving the performance of... 

    Investigation of structural and mechanical properties of magnetic pulse welded dissimilar aluminum alloys

    , Article Journal of Manufacturing Processes ; Volume 37 , 2019 , Pages 292-304 ; 15266125 (ISSN) Pourabbas, M ; Abdollah zadeh, A ; Sarvari, M ; Pouranvari, M ; Miresmaeili, R ; Sharif University of Technology
    Elsevier Ltd  2019
    Abstract
    The present study aimed to join AA4014 to AA7075 by using magnetic pulse welding (MPW). In addition, acceptable joints were achieved by selecting welding parameters such as collision angle and discharge energy appropriately. Changing collision angle and discharge energy can influence the velocity, leading to the formation of three different types of welding interfaces with wavy, molten wavy and porous morphologies. The formation of these various morphologies is mainly associated with different collision angle parameters. The hardness of the welding interface with molten layer was significantly higher than that of the base metals due to the grain refinement phenomenon occurring through the... 

    Buffer Modeling and Optimization for NSoLT (Near Speed of Light Transmission)in Future Technologies

    , M.Sc. Thesis Sharif University of Technology Shahhosseini, Sina (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    As the transistors’ dimensions in integrated circuits shrink, according to Moore’s law, a number of challenges emerges that can decrease the benefits of scaling. One of the main challenges in deep submicron CMOS technologies is the delay in interconnects. In recent years, researchers have been looking into different methods to minimize the delay in interconnects. International Technology Roadmap for Semiconductors (ITRS) predicts that the input capacitance of a buffer will become in the order of 10s of aFs with technology scaling. This will give us the opportunity to transmit the data in electrical interconnects near the speed of light.In this thesis, a novel buffer is designed in which the... 

    Interconnect Modeling and Optimization for NSoLT (NearSpeed of Light Transmission)in Future Technologies

    , M.Sc. Thesis Sharif University of Technology Rasekh, Amin (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Several advantages and problems associated with technology scaling. One of the most important problems facing technology scaling is interconnects. As technology scales down wire delay becomes dominant. Optical interconnects has been subject of many researches for more than two decades to overcome this problem. The key idea behind near speed of light transmission (NSoLT) is that for buffers at the end of ITRS projections input capacitances could be as small as tens of atto Farads. Hence, voltage of the end of global wires could jump at the time of flight.
    In this project, a global wire has been divided in to k segments in a way that data can be transferred with the speed close to the... 

    Comparison of Electrical and Optical Links in Terms of Delay/Bit-Rate/Power Dissipation as GSI Interconnects

    , M.Sc. Thesis Sharif University of Technology Shokouhi, Samad (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Today, the internal connections of the CPUs with a few billion wired transistors in 14 copper layers on the silicon wafer are possible. Recently, power dissipation has slowed the growth rate of clock growth in CPUs, and nowadays sometimes more than 60% power is lost in connections. In this situation, the increase in efficiency has been achieved in accordance with Moore's law with multi-core chips. This theme has made the connections between the cores much more important than before. Usually the information in the network structure on chip (NOC) is transmitted on these connections. Therefore, all three aspects of delay, power dissipation and bit rate are important for communication channels.... 

    Fabrication and Characterized of Transmission Line Parametrs for GNR Interconnect

    , M.Sc. Thesis Sharif University of Technology Reihany, Omid (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    The process of contracting the chips will lead the increasing of impurity concentration, decreasing the bias voltage and threshold voltage to make stable the electrical field. For using the advantage of lesser dimensions of the total circuit using decreasing bias voltage lead the dimension of the wires to be decrease also. Therefore, once the parasitic effects of wires, the RC delays of wires and the noise of power transmission will enhance obviously. With this contracting by process, electrical resistance of interconnect will enhance also. The reason of this matter is that the area chip will decrease significantly. While the operational frequency increases the effect of inductance should be... 

    Modeling of Turbulent Combustion at Supercritical Condition, Using Flamelet Based Models

    , M.Sc. Thesis Sharif University of Technology Sarvari, Ali (Author) ; Farshchi, Mohammad (Supervisor)
    Abstract
    Turbulent combustion at supercritical condition have a considerable effect in modern high performance rocket propulsion systems, gas turbines and diesel engines. In such a reaction conditions, an abrupt changes occur in thermodynamics and transport properties of fluid. So numerically modeling of a real fluid behavior of the cryogenic propellants and the turbulent trans-critical mixing and combustion processes faces serious challenges.In this study, in order to realistically represent turbulence–chemistry interactions, detailed chemical kinetics and real-fluid thermodynamic behaviors related to the gaseous hydrogen and cryogenic liquid oxygen combustion under supercritical pressures, the... 

    Simulation of HEMT (High Electron mobility Transistor) for Communication Applications

    , M.Sc. Thesis Sharif University of Technology Tahmasebi, Marzie (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    In this thesis, the simulation of HEMT for high frequency applications has been explored. It has been tried to examine the changes such as: gate recess, T-shaped gate, changing the channel length and doping of buffer layer on the performance of the proposed device. Simulation results show that the best way to improve the device performance, in particular its cut-off frequency, is increase in buffer layer doping density. Because it significantly increase the saturation current, electron mobility inside the channel, the transconductance and the cut-off frequency. If we need to lower the noise, the T-shaped gate can also be used. Also, by change in doping of donor layer, amount of 1017 cm-3 is... 

    Performance Optimization of Cu Wires for Network-on-chip Based Many-core Architectures

    , M.Sc. Thesis Sharif University of Technology Radfar, Farzad (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    The exponential increase in power density within a chip due to higher frequency of operation in recent years (Moor's law) is a major limiting factor for designers. Increasing the number of parallel cores instead of increasing the frequency of operation is a possible solution. The design of connections within the cores can be followed by the old process but the global interconnectsbetween the cores instead of point to point can be replaced byNetwork-on-Chip (NoC). In this thesis, The dimensions of global interconnects in many-core chips are optimized for maximum bandwidth density and minimum delay taking into account network-on-chip router latency and size effects of coppe. The optimal... 

    Piece-wise Linear Approximation of Step Response for GSI Interconnects

    , M.Sc. Thesis Sharif University of Technology Benam, Majid (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Since interconnects are playing a very important role in today’s IC technology, introducing new models and approximations is vital to IC designers. In this dissertation, maxwell equations are introduced as they are the main equations governing transmission lines. Different methods to model interconnects are also presented. Moreover, because of the importance of the step response of a system, available methods for finding the step response of interconnects are briefly discussed. Some approximations are also described, which result in faster but not very accurate responses. Delay and noise in integrated circuit connections have been the subject of several investigations for a long time. Since... 

    Increasing Bit-Rate of a Lossy Channel By Re-shaping of the Input Signal

    , M.Sc. Thesis Sharif University of Technology Bootaki, Bahram (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Due to the growth of information volume and increment in the speed of processor units, it is critical to achieve higher speed in data transaction systems. This necessity could be recognized in all fields, from digital data transactions on a chip and among its building blocks to data transactions among electronic boards and computerized systems in huge control constructions.
    Methods of data transmission have been improved both in terms of speed and simplicity for different applications in today’s enormous consumer electronics market. One possible option is to use conventional wires as physical channel of transmission system.
    The most important drawback of the wires is their relative... 

    NumericalModel for Surface Scattering and Grain Boundary Scattering of Metallic Wires

    , M.Sc. Thesis Sharif University of Technology Abbaspour, Elhame (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Recently, the size of copper interconnects is going to reach lower than the mean free path of electrons for copper. In this situation, we should consider the effect of other scattering mechanisms as well as thermal scattering on copper thin films. In this work we study both DC size effect and anomalous skin effect on resistivity by a Monte Carlo method. Contribution of each scattering mechanism and the interaction between them are analyzed separately. The structure of electrical field and distribution of current in thin films have also been studied. Investigating of the effect of exact nature of surface scattering and grain boundary scattering on resistivity is one of the interests of this... 

    Design of Power Distribution Network in 3D ICs Thesis Submitted

    , M.Sc. Thesis Sharif University of Technology Zabihi, Masoud (Author) ; Sarvari, Reza (Supervisor)
    Abstract
    Delay of Interconnects in modern digital ICs is several times greater than delay of gates. One proper measure for this problem is to shorten interconnects length by using three dimensional structures instead of conventional two dimensional structures. In these structures TSVs (Through Silicon Vias) make connection between stratums. Power integrity in 3D ICs necessitates power distribution networks to have minimum IR drop and Ldi/dt noise. In this dissertation we design power distribution network considering IR drop and Ldi/dt noise margin. We expand a mathematical model which represents differential equation of power distribution in the surface of each stratum. Using this expanded model we...