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sharifkhani--mohammad
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H.264 Decoder for Portable Application
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
As mobile multimedia services become popular, it is expected that mobile devices provide more multimedia functions such as real-time video playback, TV watching, and video games. However, real-time video applications running on mobile devices are heavily constrained by their limited computing power, compared to high-end consumer devices. In order to playback a high resolution video on mobile devices, a typical approach would be to fully decode video bitstream into the pixel-domain, and then spatially downscale the decoded frames at a desired resolution. However, due to large computation and memory required for decoding followed by downscaling, this approach is unsuitable for real-time video...
Video Shot Boundary Detection
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Digital video is one of the biggest part of digital data. The first step of digital video analytics is shot boundary detection. We used overlapped partitioning beside color histogram in uncompressed data and macroblock type prediction in compressed data as feature and supervised classifiers for decision making. Tests on TRECVID 2006 shows 8.9% improvement of F-measure in uncompressed video and 5.3% in h.264 bitstream. Supplementary test is done on IRIB dataset which shows 5.7% improvement of F-measure in uncompressed and 3.2% in H.264. H.264 based algorithm is almost 7 times faster in comparison to the algorithm that includes decoding
Design and Implementation of Low Power Delta Sigma Modulator for Audio Application
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
iN This thesis, Design and implementation of a low voltage, low power Delta-Sigma Modulator (DSM) is presented. System level considerations have been discussed thoroughly. In addition a systematic design flow in the context of continuous time delta sigma modulators is provided. While voltage-domain signal processing becomes more difficult in deep sub-micron processes, a finer time resolution is achievable. Time-domain quantizers can ameliorate the design challenges of flash quantizers which arises from lower supply voltages and higher fraction of comparator metastable region. VCO based quantizer such as voltage to frequency and voltage to phase considered as time domain quantizers can be a...
Design and Simulation of a Dedicated Analog Circuit to Protect against Power Analysis Attack
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
With the rapid development of the communication technology, the demand for secure data transferring is inevitable. In this regard, all of secure systems such as Sim-Cards, Smart Cards, to name but a few, enjoy crypto hardware in order to encrypt data. The palpitating heart of these apparatuses, that is, processor, is based on well-known cryptographic algorithms such as AES, RSA, etc. In short, the security depends on the hidden key and in e. g., AES-128 bit, time to disclose the key is in order of 2128. Therefore, no computer can disclosure it in that this period is approximately equivalent to 1032 years in case of the processing computer runs on a 1GHz clock frequency, and a try-out of a...
Analysis and Design of a High Speed Embedded SRAM
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
SRAM has a very wide application in different platforms including Cache Memory in Microcontrollers, etc. also SRAM is the first candidate for memory usage in every application needing High speed or static memory circuits. SRAM Cells are constructed by Minimum size transistors in each technology node and usually the newest technology nodes are used for building SRAM blocks for accommodating maximum number of SRAM Cells in a specific area. Going through smaller technology nodes, Leakage current and Process variations problem, creates serious difficulties in designing Low Power or High speed SRAM Memories and many academic and industrial works are done wishing for improvement in SRAM power...
Design new Video Fingerprinting Algorithm
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Digital videos is one of biggest parts of digital world. With rapid development of social networks, it is more challenging to protect media against copy right violations. Video fingerprint algorithms is one of the best tools which help detecting these violations. In this thesis, we propose two algorithms in compressed and uncompressed domains which are based on dividing videos in shots. We apply our algorithms on H264 Compression standard. In compressed domain, we use frame size in bytes in stream of video for extracting fingerprints. In Uncompressed domain, we apply multi kernel algorithm in image pyramid to extract fingerprint from videos. Results from Testing on our Dataset including 1278...
A Computer Automated Design Tool for Low Power Pipelined ADC
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
During recent years the main concern of analog designers is to get the most use of Computer Aided Design (CAD) tools for design procedures.Thus the main purpose of this thesis is to introduce a very fast and precise CAD tool for the design of pipelined analog to digital converters (ADC). This is accomplished by utilizing some simulation and optimization based CAD tools at the same time. In the optimization part, the conventional numerical methods are replaced with the proposed analytical approaches. Also, anew algorithm is used in the simulation part, which makes the monte-carlo simulation to be faster compared to the conventional cases. To verify the accuracy of CAD tool performance, a...
HEVC Compressed Domain Computer Vision
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
In the first section, a novel No-Reference Video Quality Assessment (NR-VQA) method, based on Convolutional Neural Network (CNN) for High Efficiency Video Codec (HEVC) is presented. Deep Compressed-domain Video Quality (DCVQ) measures the video quality, with compressed domain features such as motion vector, bit allocation, partitioning and quantization parameter. For the training of the network, normalized PSNR is used due to the limitation of existing datasets. The evaluation of the proposed method shows that it has”96%” correlation to subjective quality assessment (MOS). The method can work simultaneously with the decoding process and measures the quality each frame in the different...
Design of a Low Power Monotonic SAR ADC with Offset Flattening
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
The successive approximation digital to analog converters are appropriate selection for use in new technologies and low-powered applications. Despite the low power consumption of this kind of converters, there are some applications like medical which require very low power consumption. In order to reduce the power consumption of SAR ADC, capacitive digital to analog converters and comparators are great importance. In this Thesis, monotonic switching method has been used, the switching power of this method is lower than the conventional method by 81.2%. Since the common mode of the output of this type of switch is variable, the offset is sensitive and requires a technique to resolve this...
An Adaptive Low-Power Sense Amplifier with Offset-Cancellation for High-Speed SRAM
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. This reinforces the need to design a more compact SRAM. With the increase in the processors speed, memories speed needs to be increased to enhance the overall throughput. Current Sense Amplifiers have partially solved the problem. However the area occupied by these amplifiers is still a large amount. The input offset is also not negligible. Due to their cascode configuration, these circuits cannot be scaled with the voltage scaling. In this thesis we proposed a new hybrid sense amplifier with an added phase, so the input offset can be cancelled with a large...
An Optimized Automated Design Algorithm for Pipeline ADC
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Analog to digital converters with different specifications are widely used in modern electronic circuits. The significant demand on pipeline converters in several low power applications is mainly due to their high speed and high resolution characteristics. Fast and simple design of analog circuits using CAD tools, is highly sought after by integrated circuit designers. In this thesis, pipeline analog to digital converters is studied and a CAD tool is proposed for transistor level design and optimizations. The main advantage of this design in comparison with the previous works is that the yield and power consumption are considered as optimization factors. The module operates in three parts:...
A Novel Bitline Leakage-Free Current Sense Amplifier with Offset Cancelation for Sub-Threshold SRAM
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
A significant large amount of modern SOCs is occupied by SRAMs. Nowadays more than 70% of the Microprocessor area is occupied by SRAMs. The fast growth of battery-operated portable applications has compelled the SRAM designers to consider subthreshold operation as a viable choice to reduce the power consumption. In most such applications, the speed of the SRAM is not the challenging parameter therefore the thrust toward low power design influence the design choices in various parts of the SRAM architecture. With technology scaling to the nanometer, Bitline leakage current and offset voltage deteriorate SRAM reading performance since SRAM cell current is close to the Bitline leakage current....
Efficient Circuit and Systematic Design of Successive Approximation Register Analog to Digital Converters
, Ph.D. Dissertation Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Successive Approximation Register (SAR) Analog to Digital Converter (ADC) converts an analog signal to a digital code based on binary search. In contrast to other converters, such as Pipeline and Flash ADCs, most of the SAR ADC components are digital, hence, SAR ADC is technology scalable. Therefore, designed using smaller tehcnologies, SAR ADCs are able to operate at a higher frequency with a lower power consumption and area. The main focus of this thesis is to reduce power consumption, although the proposed techniques and circuits are able to improve other features such as precision, area, or speed.Considering Digital to Analog Converter (DAC), a low-power structure and a novel method to...
Analysis and Development of Quality Assessment Methods of 360 Videos
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Virtual Reality technologies and its related standards and tools, will play a remarkable role in our future digital life. Development of that topic will be definitely dependent on availability of a reliable, precise and low-cost video quality assessment method. In recent years, there was a significant amount of research works on 360 videos, notably among them are new video quality metrics. Unfortunately in terms of correlation to subjective scores, they are still far from ideal especially with respect to previous performances in regular video domain. In this research we focused on desiging a full-reference 360-video quality assessment method. First, we extracted 2D viewport videos from the...
Design and Simulation of Bioimpedance Chip for Monitoring Heart Failure
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Cardiovascular disease is one of the leading causes of death and mortality. among these diseases, heart muscle inability, especially acute decompensated heart failure is very common. There are several methods to diagnose and monitor this disease, but a method that is accurate, non-invasive, portable and easy to access and easy to measure without multiple visits to the clinic; Priority for use. Early detection and continuous monitoring of fluid status by measuring the bio-impedance (Bio-Z) measurement of thoracic magnitude or phase is critical in reducing the mortality of chronic heart failure (CHF) patients. In this dissertation, for monitoring chronic heart failure, bio-impedance chips with...
Design of Integrated Circuit to Extract Energy from Piezoelectric Devices
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
Energy harvesting from wasted environmental energy to power low-power electronic devices has emerged as an enabling technology for wireless applications in the past decade. The purpose of this technology is to provide remote power sources and/or recharge storage devices such as batteries and capacitors. This concept has environmental implications in reducing chemical waste produced by replacing batteries and potential monetary benefits that also reduce maintenance costs.Energy harvesting (EH) from untapped natural energy sources is common nowadays due to the increasing demand for electricity. Sources have the potential to generate micro to milliwatt power, depending on environmental...
Implementation of the Digital Part of DVB-T Protocol with Reduced Power and Area
, M.Sc. Thesis Sharif University of Technology ; Hessabi, Shaahin (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
Abstract
An implementation of Digital Section of a DVB-T receiver has been introduced in this research. Nowadays, low-power and area-efficient designs have proven their importance in IC design aspect, so many low-power and area efficient approaches have been considered in this implementation. This design has been segregated into independent blocks, and each of them has been designed respect to the design goals. After that, all these blocks linked together and a whole system design implemented in gate level, then downloaded into a FPGA (Field programmable Gate Array) to test the timing and functionality of implemented blocks. In this thesis, some innovations have been introduced. A new algorithm for...
Power Analysis of Smartcards
, M.Sc. Thesis Sharif University of Technology ; Salmasizadeh, Mahmoud (Supervisor) ; Sharifkhani, Mohammad (Supervisor)
Abstract
For authenticity and confidentiality of data in design of smartcards, cryptographic algorithms are mainly used. These cryptographic algorithms are the base of secure communication, so they have been created to be resistant to theorical and mathematical analysis.
However, Implementation of these algorithms in electronic systems and devices such as smartcards lead to leak of information. This leaked information, known as side channel, can be utilized to reveal secret characteristics of system. Apparently, power consumption of device is most important side channel and gained a lot of attention from designers and attackers.
Hence, investigating methods of side channel attacks,...
However, Implementation of these algorithms in electronic systems and devices such as smartcards lead to leak of information. This leaked information, known as side channel, can be utilized to reveal secret characteristics of system. Apparently, power consumption of device is most important side channel and gained a lot of attention from designers and attackers.
Hence, investigating methods of side channel attacks,...
Low-Power Reconfigurable Pipeline ADC for Multi-Standard Communication
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor) ; Shoaee, Omid (Co-Advisor)
Abstract
With the rapid development of wireless communication standards, the co-existence of multiple standards in a single chip becomes inevitable. It is also fueling interest in analog to digital converters (ADCs) that are reconfigurable over a wide range of bandwidths and resolutions with adaptive power consumption. Employing such ADCs rather than using multiple individually power-optimized ADCs results in a great reduction of silicon area. Hence, a reconfigurable ADC can reduce time to market, and save costs.
This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The...
This thesis addresses the challenges exists in conventional reconfigurable methods, and presents a novel reconfiguration methodology for changing resolution in pipeline ADCs. The...
Circuit & Systematic Design of Low Power & High Speed SAR ADC
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor)
Abstract
SAR ADC is a data converter which is based on binary search to convert an analog signal to a digital signal. Unlike other converters like pipeline, most of its constituent parts are digital, and hence scalable with process and consume less power, moreover can have better speed and power performance. With advanced technologies, namely 45nm and 32 nm CMOS, SAR ADCs are preferable as they consume much less power and area, therefore well-suited for portable applications, as opposed to Flash and Pipleline converters.
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...
The main drawback of this type of converter is its limited speed which is due to the fact that one clock cycle is required to evaluate each bit. As a result, there is a...