Sharif Digital Repository

In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE  

A low-power delay-locked loop (DLL)-based clock and data recovery (CDR) circuit with a high-frequency tolerance is presented. The design of DLL clock generator is based on an analytical approach to satisfy the jitter requirements of the system. Meanwhile, a novel analogue phase interpolator (PI) has been employed for fine delay adjustment of the recovered clock. Using a charge-pump-based PI, it is possible to simplify the control circuit considerably and hence reduce the system power consumption. To improve the frequency-tracking ability of the system, a frequency control loop is also added to the proposed CDR system. Designed in conventional 0.18 μm CMOS technology and operating in 10 Gbps... 

The design of a Gm-C filter for High-Frequency applications is described in this paper. A low-pass, sixth-order elliptic Gm-C filter based on the new biquadratic architecture in 0.18 um CMOS process is designed with the proper dynamic rang. A simple structure of the high Q biquadratic filter is used to enhance the linearity and tunability of the filter. The cut off frequency of this filter is 33 MHz. It has a THD of -45 dB for 0.2 Vpp, 8 MHz signal. The complete filter including on-chip tuning circuit consumes only 0.8mA with 1.8 V single supply voltage. ©2006 IEEE  

A technique to reduce close-in phase noise in CMOS LC voltage controlled oscillators is proposed. In CMOS differential LC oscillators, the up-conversion of flicker noise mainly determines the close-in phase noise. The flicker noise of the bias current is a major component contributing to the overall low frequency noise. In this paper, a switched biasing technique to suppress the flicker noise of the bias circuit is presented. A 1.8v 2.4GHz differential LC VCO is designed in a 0.18u CMOS technology using this technique. With the proposed switching technique, the close in phase noise is improved as much as 15dB at 500 kHz offset. The simulated phase noise at the offsets of 500 kHz and 1 MHz is... 

We present a complete top-down design of a low-power multi-channel clock recovery circuit based on gated current-controlled oscillators. The flow includes several tools and methods used to specify block constraints, to design and verify the topology down to the transistor level, as well as to achieve a power consumption as low as 5mW/Gbit/s. Statistical simulation is used to estimate the achievable bit error rate in presence of phase and frequency errors and to prove the feasibility of the concept. VHDL modeling provides extensive verification of the topology. Thermal noise modeling based on well-known concepts delivers design parameters for the device sizing and biasing. We present two... 

In this paper, a fourth-order, 3.5-MHz, low-pass elliptic Gm-C filter employing low-noise, low-voltage transconductance amplifiers is presented. A new technique to enhance the linearity of the Gm-C filter is proposed. Furthermore, the nonlinear behavior of the filter caused by nonlinear behavior of transconductors with determined input amplitude is discussed. HSpice simulation results of the 1.8-V filter in a 0.18μm CMOS process show a THD of less than 44dB for 0.6Vpp input signal and an input-referred noise of less than 45 nV/√Hz in worst case. The current consumption of each OTA is 1.5-mA. © 2006 IEEE  

This paper presents a top-down approach to the design of all-silicon CMOS-based fully integrated optical receivers. From the system-level requirements, we determine the optimum block-level specifications, based on which the individual building blocks are designed. Measurement results of the manufactured design show operation at data rates exceeding 2.5-Gbps/channel for the detector, the amplification and the clock and data recovery circuits. This proof of concept is the first step towards design optimized, completely integrated, multi-channel optical receivers for high-bandwidth short-distance chip-to-chip interconnects. © 2006 IEEE