Sharif Digital Repository

This paper analyzes the problem of transient-error recovery of several protecting techniques used in fault-tolerant cache memories. In this paper, reliability and mean-time-to-failure (MTTF) equations for several protecting techniques are derived and estimated. The results of the considered techniques are compared with those of cache memories without redundancies and with only parity codes in both tag and data arrays of caches. Depending on the error rate under which a cache memory will operate, and the size of the cache memory, one of the analyzed cases could be used. If the transient-error rate is very small or the size of cache memory is relatively small, then a protected with only single... 

This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using... 

This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using... 

In this paper, a parallel algorithm is presented for data clustering on a multicomputer with star topology. This algorithm is fast and requires a small amount of memory per processing element, which makes it even suitable for SIMD implementation. The proposed parallel algorithm completes in O(K+S2-T2) steps for a clustering problem of N data patterns with M features per pattern and K clusters where S and T are the minimum numbers such that NM≤S! and KM≤T!, on the S-dimensional star graph  

This paper presents a high level method called Matrix code to protect SRAM-based memories against multiple bit upsets. The proposed method combines hamming code and parity code to assure the reliability of memory in presence of multiple bit-upsets with low area and performance overhead. The method is evaluated using one million multiple-fault injection experiments; next reliability and MTTF of the protected memories are estimated based on fault injection experiments and several equations. The fault detection/correction coverage are also calculated and compared with previous methods i.e., Reed-Muller and hamming code. The results reveal that the proposed method behaves better than these... 

In this paper, we present an experimental evaluation of transient effects on an embedded system which uses SRAM-based FPGAs. A total of 7500 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD) and a simple 8-bit microprocessor was implemented on the FPGA as the testbench. The results show that nearly 64 percent of faults cause system failures and about 63 percent of the faults lead to corruption of the configuration data of the FPGA chip. © 2005 IEEE  

This paper presents an experimental evaluation of transient effects on SRAM-based FPGAs. A total of 9000 transient faults were injected into the target FPGA using Power Supply Disturbances (PSD). The results show that nearly 60 percent of faults cause system failures and about 58 percent of the faults lead to corruption of the configuration data of the FPGA chip. © 2005 IEEE  

The technology of SRAM-based devices is sensible to Single Event Upsets (SEUs) that may be induced mainly by high energy heavy ions and neutrons. This paper presents a framework for the evaluation of fault-tolerant designs implemented on SRAM-based FPGAs using emulated SEUs. The SEU injection process is performed by inserting emulated SEUs in the device using its configuration bitstream file. An Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used to experimentally evaluate the method. The results show that between 32 to 45 percent of SEUs injected to the device propagate to the output terminals of the device  

SRAM-based FPGAs are currently utilized in applications such as industrial and space applications where high availability and reliability and low cost are important constraints. The technology of such devices is sensible to Single Event Upsets (SEUs) that may be originated mainly from heavy ion radiation. This paper presents a fault injection method that is based on emulated SEU on the configuration bitstrearn file of commercial SRAM-based FPGA devices to study the error propagation in these devices. To demonstrate the method, an Altera FPGA, i.e. the Flex10K200, and the ITC'99 benchmark circuits are used. A fault injection tool is developed to inject emulated SEU faults into the circuits.... 

Mesh-based interconnection networks are the most popular inter-processor communication infrastructures used in current parallel supercomputers. Although many analytical models of n-D torus interconnection networks have been reported in the literature over the last decade, few analytical models have been proposed for the 2-D mesh case (and not for the general n-D mesh network) using inaccurate approximations as they have not fully incorporated the asymmetry effects of the mesh topology, in order to reduce the model complexity. There has not been reported, to the best of our knowledge, a performance model that can deal with the n-D mesh network. To fill this gap, in this paper, we propose the... 

Mesh-based interconnection networks are the most popular inter-processor communication infrastructures used in current parallel supercomputers. Although many analytical models of n-D torus interconnection networks have been reported in the literature over the last decade, few analytical models have been proposed for the 2-D mesh case (and not for the general n-D mesh network) using inaccurate approximations as they have not fully incorporated the asymmetry effects of the mesh topology, in order to reduce the model complexity. There has not been reported, to the best of our knowledge, a performance model that can deal with the n-D mesh network. To fill this gap, in this paper, we propose the...