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3d-capacitance
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Accelerating 3-D capacitance extraction in deep sub-micron VLSI design using vector/parallel computing
, Article 13th International Conference on Parallel and Distributed Systems, ICPADS, Hsinchu, 5 December 2007 through 7 December 2007 ; Volume 2 , December , 2007 ; 15219097 (ISSN); 9781424418909 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
2007
Abstract
The widespread application of deep sub-micron and multilayer routing techniques makes the interconnection parasitic influence become the main factor to limit the performance of VLSI circuits. Therefore, fast and accurate 3D capacitance extraction is essential for ultra deep sub-micron design (UDSM) of integrated circuits. Parallel processing provides an approach to reducing the simulation turn-around time. In this paper, we present parallel formulations for 3D capacitance extraction based on P-FFT algorithm, on a personal computer (PC) or on a network of PCs. We implement both vector and parallel versions of 3D capacitance extraction algorithm simultaneously and evaluate our implementation...