Sharif Digital Repository

This paper presents the design of a 6-bit active digital phase shifter in 0.18-μm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5 GHz. The average voltage gain ranges from 1.7 dB at 2.4GHz to -0.14 dB at 5 GHz. Input P1 dB is typically 1.3±0.9 dBm at 3.5 GHz for overall phase states  

An innovative vector-sum phase shifter with a full 360° variable phase-shift range in 0.18-μm CMOS technology is proposed and experimentally demonstrated in this paper. It employs an I/Q network with high I/Q accuracy over a wide bandwidth to generate two quadrature basis vector differential signals. The fabricated chip operates in the 2.3-4.8 GHz range. The root-mean-square gain error and phase error are less than 1.1 dB and 1.4° over the measured frequency span, respectively. The total current consumption is 10.6 mA (phase shifter core: ∼2.6 mA) from a 1.8 V supply voltage and overall chip size is 0.87 × 0.75 mm 2. To the best of the authors' knowledge, this circuit is the first... 

In this paper, a low power active phase shifter in 0.18 μm CMOS technology, operating from 5 to 6 GHz, for WLAN applications is presented. Design equations for this novel structure, which consists of two current steering stages, transconductance stage and DACs, are derived, thoroughly. This phase shifter has a range of 360° with 5.625° phase resolution. The power consumption is 35 mW. The RMS phase error is only 0.3°. The simulated power gain, input P1dB, and NF are 4 dB, -0.8 dBm and 6 dB, respectively