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    Improving the energy/power consumption of parallel decimal multipliers

    , Article Indian Journal of Science and Technology ; Vol. 7, issue. 3 , 2014 , p. 276-281 Malekpour, A ; Ejlali, A ; Sharif University of Technology
    Abstract
    Decimal arithmetic has gained intensive attention in the last decade. Most commercial, financial, scientific, and internet-based applications need their data to be precise, while binary number system loses preciseness in some cases. The latency and area are two major factors in existing research works on decimal multiplication. However, energy/power consumption is another important factor in today's digital systems. Hence, in this paper we proposed a new low power decimal adder based on prediction technique for decreasing the energy/power consumption of parallel decimal multiplication and show its impacts on one of the well-known parallel decimal multipliers architecture. Our observations... 

    A low cost circuit level fault detection technique to full adder design

    , Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN) Mozafari, S. H ; Fazeli, M ; Hessabi, S ; Miremadi, S. G ; Sharif University of Technology
    2011
    Abstract
    This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition  

    FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications

    , Article Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors ; 2013 , Pages 153-159 ; 10636862 (ISSN) ; 9781479904921 (ISBN) Hajkazemi, M. H ; Baniasadi, A ; Asadi, H ; Sharif University of Technology
    2013
    Abstract
    This paper introduces an alternative Fault-Tolerant Power-Aware Hybrid Adder (or simply FARHAD). FARHAD is a highly power efficient protection solution against errors in application with high number of additions. FARHAD, similar to earlier studies, relies on performing add operations twice to detect errors. Unlike previous studies, FARHAD uses an aggressive adder to produce the initial outcome and a low-power adder to generate the second outcome, referred to as the checker. FARHAD uses checkpointing, a feature already available to high-performance processors, to recover from errors. FARHAD achieves the high energy-efficiency of timeredundant solutions and the high performance of... 

    A low-cost fault-tolerant technique for carry look-ahead adder

    , Article 2009 15th IEEE International On-Line Testing Symposium, IOLTS 2009, Sesimbra-Lisbon, 24 June 2009 through 26 June 2009 ; 2009 , Pages 217-222 ; 9781424445950 (ISBN) Namazi, A. R ; Sedaghat, Y ; Miremadi, G ; Ejlali, A. R ; Sharif University of Technology
    2009
    Abstract
    This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques. © 2009 IEEE  

    A high speed and low cost error correction technique for the carry select adder

    , Article International Conference on Availability, Reliability and Security, ARES 2009, Fukuoka, Fukuoka Prefecture, 16 March 2009 through 19 March 2009 ; 2009 , Pages 635-640 ; 9780769535647 (ISBN) Namazi, A ; Miremadi, S. G ; Ejlali, A ; Sharif University of Technology
    2009
    Abstract
    In this paper, a high speed and low cost error correction technique is proposed for the Carry Select Adder (CSA) which can correct both transient and permanent errors and is applicable on all partitioning types of the basic CSA circuit. The proposed error correction technique is compatible with all existing error detection techniques which are proposed for the CSA adder. The synthesized results show that applying this novel error correction technique to a CSA with error detection technique results in up to 18.4%, 3.1% and 14.9%, increase in power consumption, delay and area respectively. © 2009 IEEE  

    Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors

    , Article Microelectronics Reliability ; Volume 51, Issue 12 , December , 2011 , Pages 2374-2387 ; 00262714 (ISSN) Fazeli, M ; Namazi, A ; Miremadi, S. G ; Haghdoost, A ; Sharif University of Technology
    2011
    Abstract
    This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

    A body biasing method for charge recovery circuits: Improving the energy efficiency and DPA-immunity

    , Article Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, 5 July 2010 through 7 July 2010 ; July , 2010 , Pages 195-200 ; 9780769540764 (ISBN) Khatir, M ; Ejlali, A ; Sharif University of Technology
    2010
    Abstract
    Charge recovery is a promising concept to design (cryptographic) VLSI circuits with low energy dissipation. However, unsatisfactory designs of proposed logic cells degrade its theoretical efficiency significantly both in its energy consumption and the resistance against differential power analysis attacks (DPA-attacks). Short circuit dissipation and non-adiabatic discharging of capacitance loads are the two major sources of this degradation which are addressed in this paper. In order to reduce these dissipation significantly, we manipulate threshold voltage of circuits transistors by body biasing. To evaluate the efficiency of our method we select a common charge recovery logic called 2N2N2P... 

    Low-power Design of Decimal Multipliers

    , M.Sc. Thesis Sharif University of Technology Malekpour, Amin (Author) ; Ejlali, Ali Reza (Supervisor)
    Abstract
    Decimal multiplication is a frequent operation with inherent complexity in implementation. Commercial and financial applications require their data to be precise while binary number system cannot ensure precision. Existing research works on parallel decimal multipliers have mainly focused on latency and area as two major factors to be improved. However, energy/power consumption is another prominent issue in today’s digital systems. Hence, in this thesis we present a comparative study of parallel decimal multipliers, considering energy/power consumption (leakage and dynamic power consumption), latency and area. Furthermore, we present two novel techniques to reduce energy/power consumption of... 

    A novel design of hybrid-time-interleaved current steering digital to analog converter and its behavioral simulation considering non-ideal effects

    , Article Integration ; Volume 69 , 2019 , Pages 321-334 ; 01679260 (ISSN) Sariri, H ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
    Elsevier B.V  2019
    Abstract
    This work presents a behavioral model for non-ideal effects in a novel Hybrid time-interleaved digital to analog converter (TIDAC). In Hybrid DACs, both ΔΣ and Nyquist structures are used. In this work, in the Nyquist path, the 2-time-interleaving technique is used and in the ΔΣ path, a new structure is proposed to reduce the critical path in the TI delta-sigma modulator (DSM). In conventional TIDSM, adding each channel to the structure leads to increasing the critical path as one full-adder. This, in turn, decreases the speed of modulator since a single feedback loop is utilized to compute the running sum of the input signals. In this work, a new type of poly-phase decomposition is... 

    Sub-threshold charge recovery circuits

    , Article Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 3 October 2010 through 6 October 2010, Amsterdam ; 2010 , Pages 138-144 ; 10636404 (ISSN) ; 9781424489350 (ISBN) Khatir, M ; Mohammadi, H. G ; Ejlali, A ; IEEE; IEEE Circuits and Systems Society; IEEE Computer Society; HiPEAC Compilation Architecture ; Sharif University of Technology
    2010
    Abstract
    Embedded systems account for wide range of applications. However, the design of such systems is faced with a diverse spectrum of criteria. The energy consumption, performance, and demanding security concerns are some of the most significant challenges in designing of such systems. With these challenges, the design process can be managed more easily if a flexible logic circuit with the ability of satisfying the abovementioned concerns is taken into account. To achieve such a logic circuit, in this paper we have combined the sub-threshold operation and charge recovery techniques. Using our technique, lower power consumption, ability of operating at higher frequencies, and more security (to... 

    Efficient design of a coplanar adder/subtractor in quantum-dot cellular automata

    , Article 9th UKSim-AMSS IEEE European Modelling Symposium on Computer Modelling and Simulation, EMS 2015, 6 October 2015 through 8 October 2016 ; 2015 , Pages 456-461 ; 9781509002061 (ISBN) Sangsefidi, M ; Karimpour, M ; Sarayloo, M ; Romero G ; Orsoni A ; Al-Dabass D ; Pantelous A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Scaling of CMOS devices being aggressively decreasing by reduce of transistor dimensions. However, such level of integration leads to many physical limit and transistors cannot get much smaller than their current size. Quantum-dot Cellular Automate is a novel technology which significantly reduces physical limit of CMOS devices implementation, thus, it can be an appropriate candidate to be substituted for CMOS technology. In addition to high integration density of QCA circuits, other unique specifications such as high speed and low power consumption encourage researchers to utilize this technology instead of CMOS technology. In this paper, a new layout of XOR gate is presented in QCA... 

    A formal approach for debugging arithmetic circuits

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 28, Issue 1 , 2009 , Pages 742-754 ; 02780070 (ISSN) Sarbishei, O ; Tabandeh, M ; Alizadeh, B ; Fujita, M ; Sharif University of Technology
    2009
    Abstract
    This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, XOR extraction, and carry-signalmapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted XORs into half/full-adders to make a very fast debugging algorithm. This approach is robust... 

    A formal approach for debugging arithmetic circuits

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 28, Issue 5 , 2009 , Pages 742-754 ; 02780070 (ISSN) Sarbishei, O ; Tabandeh, M ; Alizadeh, B ; Fujita, M ; Sharif University of Technology
    2009
    Abstract
    This paper presents a novel automatic debugging algorithm for a postsynthesis combinational arithmetic circuit. The approach is robust under wide varieties of arithmetic circuit architectures and design optimizations. The debugging algorithm in this paper consists of three phases of partial product initialization, xor extraction, and carry-signal mapping. The run-time complexity of conventional carry-signal-mapping algorithms, such as the approach described by Stoffel and Kunz, is exponential. However, in the proposed algorithm, by making use of some important design issues, we categorize the extracted xors into half/full-adders to make a very fast debugging algorithm. This approach is... 

    CNTFET full-adders for energy-efficient arithmetic applications

    , Article 6th International Conference on Computing, Communications and Networking Technologies, 13 July 2015 through 15 July 2015 ; 2015 ; 9781479979844 (ISBN) Grailoo, M ; Hashemi, M ; Haghshenas, K ; Rezaee, S ; Rapolu, S ; Nikoubin, T ; University of North Texas ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    Abstract
    In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm...