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    A wide dynamic range low power 2× time amplifier using current subtraction scheme

    , Article 2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016, 22 May 2016 through 25 May 2016 ; Volume 2016-July , 2016 , Pages 462-465 ; 02714310 (ISSN); 9781479953400 (ISBN) Molaei, H ; Khorami, A ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    The most challenging issue of conventional Time Amplifiers (TAs) is their limited Dynamic Range (DR). This paper presents a mathematical analysis to clarify principle of operation of conventional 2× TA's. The mathematical derivations release strength reduction of the current sources of the TA is the simplest way to increase DR. Besides, a new technique is presented to expand the Dynamic Range (DR) of conventional 2× TAs. Proposed technique employs current subtraction in place of changing strength of current sources using conventional gain compensation methods, which results in more stable gain over a wider DR. The TA is simulated using Spectre-rf in TSMC 0.18um COMS technology. DR of the 2×... 

    A low power high resolution time to digital converter for ADPLL application

    , Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) Molaei, H ; Hajsadeghi, K ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

    A mm-Wave MIMO transmitter with a digital beam steering capability using CMOS all-digital phase-locked loop chips

    , Article 2018 IEEE MTT-S International Microwave Workshop Series on 5G Hardware and System Technologies, IMWS-5G 2018, 30 August 2018 through 31 August 2018 ; 2018 ; 9781538611975 (ISBN) Salarpour, M ; Bogdan Staszewski, R ; Farzaneh, F ; Sharif University of Technology
    In this paper, we propose a mm-wave transmitter architecture intended for radar and 5G MIMO applications with beam steering over 57-63 GHz frequency band. Each transmitter chain comprises an all-digital phase-locked loop (ADPLL) CMOS IC chip intended to be dictated to a single antenna unit within an array. For demonstration purposes, each IC is embedded on a printed circuit board (PCB) to provide beam steering using highly accurate digital approach. The overall transmitter is connected to an antenna array with half wavelength spaced elements to maximize the beam scanning coverage. The ADPLL boards are fabricated and a calibration technique is carried out to align amplitude-phase of all... 

    Synchronization-Phase Alignment of All-Digital Phase-Locked Loop Chips for a 60-GHz MIMO Transmitter and Evaluation of Phase Noise Effects

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 7 , 2019 , Pages 3187-3199 ; 00189480 (ISSN) Salarpour, M ; Farzaneh, F ; Staszewski, R. B ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57-63-GHz multiple-input multiple-output (MIMO) transmitter (TX) with a digital beam-steering capability. The ADPLL TX chains are first fabricated in nanoscale CMOS and then time-synchronized and frequency-phase locked by a field-programmable gate array (FPGA) evaluation board. The calibration approach for phase alignment is carried out using a cancellation method to acquire the out-of-phase state within two ADPLLs. The accuracy of beam steering and phase alignment is investigated and analyzed based on a time-domain model for ADPLL to consider the impact of...