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Design of Low Phase Noise DCO in All Digital Frequency Synthesizers
, M.Sc. Thesis Sharif University of Technology ; Atarodi, Mojtaba (Supervisor)
Abstract
A new class of design has been introduced in the RF circuits and Frequency Synthesizers, which is based on the digital circuits. Implementation of the digital synthesizers suppresses the need to use loop filter and thus reduces the loop lock time. In this thesis different topologies of digitally controlled oscillators using inductor and capacitor tank and all digital architectures used in high frequency all digital synthesizers in 0.18um CMOS technology has been inspected and simulated. Novel techniques introduced to improve the ring oscillator-based design’s specifications which doesn’t need inductor. Using the introduced techniques, the phase noise has been lessened acceptably with respect...
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
With the advancement of the technology, Design of low power devices such as biomedical systems, wireless sensor network, portable devices and … has received more attention. Digitally controlled oscillator (DCO) is one of the sub-blocks in systems such as all digital phase locked loop (ADPLL) which consumes the major power of the system. Therefore, Design of a low power DCO will decrease the power consumption of the system significantly.
In this thesis, a digital control oscillator which is ultra low power is design for system on chip applications. Coarse-Fine architecture is used with binary weighted cells in this design. For the Coarse tuning stage, a new delay cell is proposed which...
In this thesis, a digital control oscillator which is ultra low power is design for system on chip applications. Coarse-Fine architecture is used with binary weighted cells in this design. For the Coarse tuning stage, a new delay cell is proposed which...
Synchronization-Phase Alignment of All-Digital Phase-Locked Loop Chips for a 60-GHz MIMO Transmitter and Evaluation of Phase Noise Effects
, Article IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 7 , 2019 , Pages 3187-3199 ; 00189480 (ISSN) ; Farzaneh, F ; Staszewski, R. B ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57-63-GHz multiple-input multiple-output (MIMO) transmitter (TX) with a digital beam-steering capability. The ADPLL TX chains are first fabricated in nanoscale CMOS and then time-synchronized and frequency-phase locked by a field-programmable gate array (FPGA) evaluation board. The calibration approach for phase alignment is carried out using a cancellation method to acquire the out-of-phase state within two ADPLLs. The accuracy of beam steering and phase alignment is investigated and analyzed based on a time-domain model for ADPLL to consider the impact of...
Time to Digital Converters for ADPLL Applications
, Ph.D. Dissertation Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations....
TDC & MMD Design for Bluetooth Low Energy Standard Transmitter
, M.Sc. Thesis Sharif University of Technology ; Fotowwat Ahmadi, Ali (Supervisor)
Abstract
IoE devices are going to integrate with our environment. It has been predicted that there would be more than 6 connected devices per each person by 2020. Currently what obstruct this technology from continuing its evolusion path, is its dependence on Ultra Low-Power devices, and for this reason there is a huge concenteration on Radio-Frequency standards which can make devices more power efficient. Within these standards, Bluetooth Low Energy (BLE) attracted designers consentration for its similarities with conventional Bluetooth and its dominance in cellphones and other portable devices.In this project, we have attempted to design a trasmitter for BLE standard based on an All Digital Phase...
Design and Simulation of Phase Detector and Other Digital Circuits of an All Digital Frequency Synthesizer to Decrease Phase Noise and Lock Time
, M.Sc. Thesis Sharif University of Technology ; Atarodi, Mojtaba (Supervisor)
Abstract
In this thesis, An All Digital Frequency Synthesizer for use in RF applications is designed in 180nm CMOS. Different blocks such as Phase detector, Loop filter and Loop counter is designed. Finally, an All Digital Frequency Synthesizer is modeled using this circuits and an Digitally controlled oscillator model and is designed for GSM. In this thesis a new method is proposed to noise shape the quantization noise of the time to digital converter. The Time to Digital Converter has 7mW power consumption for 0ns to 1ns input range. Using this noise shaping method, quantization noise is reduced about 20dB. Also, limit cycle related spurs is reduced significantly using first order and second order...
A noise shaped flash time to digital converter for all digital frequency synthesizers
, Article ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, 23 August 2009 through 27 August 2009 ; 2009 , Pages 898-901 ; 9781424438969 (ISBN) ; Atarodi, M ; Sharif University of Technology
Abstract
Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise
Analysis and Design of a Multiple-Input Multiple-output (MIMO) Transmitter in the 60 GHz Band with a Beam Steering Capability Using All-digital Phase-locked Loop Chip
, Ph.D. Dissertation Sharif University of Technology ; Farzaneh, Forouhar (Supervisor)
Abstract
Multiple-Input Multiple-Output (MIMO) communications at millimeter-wave (mm-wave) frequencies (e.g., in the 60 GHz band) is a modern technology recently considered for various applications, such as emerging 5G services for multi-user MIMO (MU-MIMO) and high-resolution frequency-modulated continuous wave (FMCW) MIMO radars to support multi-gigabit throughputs in short-range environments via spatial multiplexing-diversity. Nevertheless, the impairments of communication channels in this frequency band, including significant propagation loss and severe blockage effect, are quite challenging to allow an efficient communication link. Hence, beamforming/beam steering can play a crucial role in 60...