Sharif Digital Repository

This paper presents a harmonic termination technique for single-and multi-band high-efficiency class-F monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). The harmonic termination network (HTN), realized with the minimum possible number of elements, can be used to terminate an arbitrary number of harmonics in a single-band PA or harmonics of multiple frequencies in a concurrent multi-band PA. The drain and gate bias lines are embedded in the HTNs to obviate the need for RF chokes and reduce the chip area. A single-and a dual-band MMIC PA are designed using the proposed technique and implemented in a 0.25-μm AlGaAs-InGaAs pHEMT technology. The single-band 5.5-GHz PA... 

In this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design, a pass-band filter is applied at the LNA output to attenuate undesired out-of-band signals. In the proposed design, the limiter-LNA is implemented with a 0.25 µm gate length AlGaAs/InGaAs pHEMT process. Measured noise figure of chain is 2.7 dB and average gain over 8.5–9.5 GHz frequency range and... 

In this paper concurrent design of Schottky diode based limiter and low noise amplifier (LNA), based on noise matching, is investigated to achieve minimum noise figure (NF) of the receiver chain. In design procedure of the LNA, the noise figure is minimum, gain at central frequency is 14.5 dB, and limiter structure tolerates up to 5 W continuous wave input power. In the proposed concurrent design, a pass-band filter is applied at the LNA output to attenuate undesired out-of-band signals. In the proposed design, the limiter-LNA is implemented with a 0.25 µm gate length AlGaAs/InGaAs pHEMT process. Measured noise figure of chain is 2.7 dB and average gain over 8.5–9.5 GHz frequency range and... 

This paper presents the design procedure of monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs) as well as implementation of high-efficiency and compact-size HPAs in a 0.25-μm AlGaAs-InGaAs pHEMT technology. Presented design techniques used to extend bandwidth, improve efficiency, and reduce chip area of the HPAs are described in detail. The first HPA delivers 5 W of output power with 40% power-added efficiency (PAE) in the frequency band of 8.5-12.5 GHz, while providing 20 dB of small-signal gain. The second HPA delivers 8 W of output power with 35% PAE in the frequency band of 7.5-12 GHz, while maintaining a small-signal gain of 17.5 dB. The 8-W HPA chip area is 8.8... 

In this paper, a thorough design procedure for concurrent design of integrated antiparallel Schottky-diode-based limiter and low noise amplifier (LNA) is presented. The optimum number of limiter branches, the size and number of diodes in each branch, width of the transmission line loaded by diode branches, and design considerations for input transistor of the LNA are discussed in detail. To improve power handling of the limiter with a minimum impact on overall noise figure (NF), a novel limiter structure is proposed where transistors are utilized in a limiter topology. A design procedure is also introduced for the transistor-based limiter-LNA. Developed methodologies are employed to design... 

This paper presents a design methodology for class-J monolithic microwave integrated circuit (MMIC) power amplifiers (PAs). Theoretical derivations of optimum load impedances, output power, efficiency, and maximum bandwidth are described in presence of nonlinear drain-source resistance of transistors (RDS). A procedure is developed for ideal transistor sizing where transistors are concurrently stabilized and sized to achieve the maximum power-added efficiency (PAE). A 3.5-7 GHz, 0.5-W class-J PA is implemented in a 0.1-μm AlGaAs-InGaAs pHEMT technology to check the accuracy of the proposed approach. With chip dimensions of 1.57 × 1.29 mm2, the PA achieves 56% average PAE over the frequency... 

This paper presents a methodology for the design of Ka/Q-band monolithic microwave integrated circuit (MMIC) high-power amplifiers (HPAs). Design techniques are introduced to reduce chip area and to improve bandwidth (BW). These techniques are applied to the design of a 31-39-GHz 5-W HPA implemented on a 0.1-μm AlGaAs-InGaAs pseudomorphic HEMT (pHEMT) technology. With chip dimensions of 3.35 × 3.2 mm2, the HPA achieves 24% average power-added efficiency (PAE) over the frequency band, while maintaining an average 22-dB small-signal gain. A balanced high-power amplifier (BPA) is also presented, which combines the power of two 5-W HPA cells to deliver peak 8.5-W output power (Pout) in the... 

In this paper, design and analysis using analytical expressions for the inverse class-E power amplifier (PA) operating at the outside nominal operation, i.e., class-En PA, is presented. This operation is defined as non-zero current switch (n-ZCS) and non-zero derivative current switch (n-ZDCS) conditions. The generalized design equations as a function of design specifications, load-resistance and a given dc-supply voltage are derived. Two degrees of the design freedom achieved thanks to n-ZCS and n-ZDCS that are utilized for the simultaneous satisfaction of design specifications, such as peakswitch- voltage and peak-switch-current along with a given loadresistance. The output power... 

In this paper, performance of class-J mode power amplifiers (PAs) is studied when a second-harmonic voltage component is added to the input node of the device. Theoretical formulations for the optimum load impedances, output power, and drain efficiency are developed for this case, and it is shown that the inclusion of a proper second-harmonic voltage at the gate node of the transistor improves the drain efficiency and output power. To check the accuracy of the theoretical analyses and the simulation results, a proof-of-concept 1-GHz 0.65-W class-J PA is fabricated in a 0.25-μm AlGaAs-InGaAs pHEMT technology. The nonlinear gate-source capacitor (CGS) of the transistor is employed to generate... 

This paper presents two integrated concurrent dual-band class-J power amplifiers (PAs) in AlGaAs-InGaAs pHEMT technology. Design flexibility of class-J space is employed to explore the availability of a dual-band PA where the center frequency of the second band is twice the center frequency of the first band (f2=2f1). The theoretical formulations are developed for f2=2f1 case, for which it is not feasible to obtain high efficiencies using class-F-1, class-F, and other high-efficiency modes. A proof of concept 5/10-GHz class-J PA is manufactured in a 0.1- μm GaAs pHEMT technology. The proposed PA delivers 26.9- and 26-dBm output power with peak power added efficiencies (PAEs) of 49% and 46%... 

In this paper, the class-J mode of operation is investigated when sinusoidal, half-sinusoidal (HS), triangle, pulse, and reduced conduction angle voltage waveforms are shaped at the gate node of the transistor. Output power, maximum power-added efficiency (PAE), large signal gain (LSG), and load-pull contours are presented and compared for each input signal. It is shown that PAE of a class-J power amplifier (PA) is improved when an HS voltage is realized at the gate node of the transistor. This enhancement can also be observed for a pulse input with 20% duty cycle, however, at the expense of reduced output power and LSG. A proof-of-concept, two-stage class-J PA is designed and fabricated in... 

This paper presents a design procedure for a wideband 6-18-GHz monolithic microwave integrated circuit highpower amplifier (HPA) in 0.25-μm AlGaAs-InGaAs pHEMT technology. The design is mainly focused on the realization of the passive circuits to provide the required low-loss and wideband impedance transformation networks. The two-stage GaAs HPA achieves an average output power of 39.6 dBm and a peak output power of 40.5 dBm at 11 GHz, in pulsed mode operation, with a small-signal gain of S21 > 10 dB over the entire bandwidth. The average power added efficiency (PAE) is 22%, with a peak PAE of 29% at 11 GHz. The HPA chip occupies an area of 5×3.6 mm2. The achieved output power and the... 

This paper presents the design and implementation of a distributed class-J power amplifier (DJPA) in a 0.25-μm AlGaAs-InGaAs pHEMT technology. Class-J mode of operation is introduced in design of distributed power amplifiers (DPAs) to achieve high power added efficiencies (PAEs) over wide frequency ranges. Extensive load-pull (LP) and source-pull (SP) simulations are performed to show that class-J PAs are less sensitive to proper termination of higher order harmonics, and high PAE and output power can be obtained even if the second, third, fourth, and fifth harmonics comprise a real impedance. This is essential in DPAs as the higher order harmonics of the frequencies at lower side of the... 

The performance analysis of junctionless (JL) gate-all-around (GAA) metal oxide semiconductor field effect transistors (MOSFETs) is investigated using the Non-Equilibrium Green's Function (NEGF) formalism. The main problem of JL transistors is found to be the OFF-state current. In the present work, the OFF-state current of such devices is decreased by choosing channel materials with a large band gap and heavy effective mass. Our simulation results show that the OFF-state current of JL transistors with p-type GaAs is less than that of n-type GaAs. Plus, the heterostructure (HES) channel is proposed in this study for improving the device characteristics of JL-FETs as compared to homostructure... 

In this paper, design and analysis using analytical expressions for the inverse class-E power amplifier (PA) operating at the outside nominal operation, i.e., class- $ ext{E}-{mathrm{n}}$ PA, is presented. This operation is defined as nonzero current switch (n-ZCS) and nonzero-derivative-current switch (n-ZDCS) conditions. The generalized design equations as a function of design specifications, load resistance, and a given dc-supply voltage are derived. Two degrees of the design freedom achieved thanks to n-ZCS and n-ZDCS that are utilized for the simultaneous satisfaction of design specifications, such as peak-switch-voltage and peak-switch-current along with a given load resistance. The...