Loading...
Search for:
analog-front-end
0.003 seconds
A new full CMOS 2.5-V two-stage line driver with variable gain for ADSL applications
, Article 2004 IEEE International Symposium on Circuits and Systems - Proceedings, Vancouver, BC, 23 May 2004 through 26 May 2004 ; Volume 4 , 2004 , Pages IV-405-IV-408 ; 02714310 (ISSN) ; Atarodi, M ; Aslanzadeh, H. A ; Saeedi, S ; Safarian, A. Q ; Sharif University of Technology
2004
Abstract
In this paper a new low-voltage two-stage class-AB line driver for ADSL applications is presented. The new proposed line-driver consists of only two stages with a new method to control the quiescent current of the output stage. The low-voltage full-CMOS high-linear line driver shows -77 dB THD for a load as low as 20 ohms. The line driver has variable gain, attenuating the input signal from 0dB to -14dB with 2dB steps. The peak to peak differential output swing is 4.2-V from a 2.5-V Supply voltage in a 0.25um standard CMOS technology
A compact low power mixed-signal equalizer for gigabit ethernet applications
, Article ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 5167-5170 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN) ; Eghbalkhah, B ; Saeedi, S ; Afzali Kusha, A ; Atarodi, M ; Sharif University of Technology
2006
Abstract
In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE
Design and Implementation of a Passive Ku band phase Shifter in 0.18µm CMOS Process
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor)
Abstract
In this project, a “Ku” band (16.3GHz-17.3GHz) 6-bit phase shifter for realizing a phase array T/R module is designed, implemented and measured in CMOS 0.18μm technology. Design specifications for this block were: RMS phase error should be less than 2.5 degree in bandwidth, better than 12dB loss and better than 16dBm input 1dB compression point. High-pass/low-pass filter structure is used to implement this phase shifter. In order to decrease phase shift error in process and temperature corners, a new structure for one of bits was introduced. This structure is less sensitive to process and temperature corners and furthermore it conSumes less area in layout, but it has more loss variation...
Design and Implementation of Controller Area Network (CAN) Transceiver in High Voltage BCD 0.18μm Process
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor)
Abstract
In this thesis, a transceiver chip compliant to Controller Area Network (CAN) protocol has been designed and implemented in High Voltage BCD 0.18um Technology.This RX/TX chip contains a transmitter, normal and low power receivers.In the transmitter, CAN bus common-mode voltage is sampled with a voltage sampler circuit and compared with a reference voltage. Receiving a control signal, the transmitter slop control circuit varies the speed turning output transistors on and off in order to keep transmitter Electromagnetic Emission (EME) as low as possible. In the receiver, a new method for bus common mode voltage rejection is introduced. By using a V-I converter block and a current subtractor...
Design and Implementation of Local Interconnect Network (LIN)Transceiver in High Voltage BCD 0.18 um
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor) ; Faez, Ramin (Supervisor)
Abstract
In this study, a Local Interconnect Network (LIN) transceiver was designed and implemented. This chip contains transmitter, receiver, low power receiver, digital control unit, oscillator, voltage regulator, high voltage switch, temperature sensor and battery voltage detector. The main focus on this study was on designing transmitter,receiver, low power receiver and temperature sensor. Through designing of this chip, in addition to functional and physical layer specification that mentioned in ISO 17987, electromagnetic compatibility specifications have been considered significantly.The designed chip with slope control and wave shaping of BUS signal has excellent radiated emission performance....
Design and Implementation of Low-Speed Controller Area Network (CAN) Transceiver in High Voltage BCD 0.18μm Process
, M.Sc. Thesis Sharif University of Technology ; Medi, Ali (Supervisor)
Abstract
In this thesis, a Fault-Tolerant Low-Speed Controller Area Network (CAN) transceiver chip has been designed and implemented in High Voltage BCD 0.18um technology. The designed transceiver is compliant to ISO 11898 functional standard, TJA1055 datasheet as a reference chip, as well as the standards related to Electro-Magnetic Compatibility (EMC). Its failure management capability is completely based on the measurement results of the reference chip. All the characteristics of the designed transceiver, after two constructions, were measured using three types of test boards, in addition to room temperature in chambers with temperatures of -40 °C and 125 °C.This transceiver has a normal mode and...