Sharif Digital Repository

In this paper, we propose a low power register file architecture for embedded processors. The proposed architecture, "Value-Aware Partitioned Register File (VAP-RF)", employs a partitioning technique that divides the register file into two partitions such that the most frequently accessed registers are stored in the smaller register partition. In our partitioning algorithm, we introduce an aggressive clock-gating scheme based on narrow-value registers to furthermore reduce power. Experimental results on an ARM processor for selected MiBench workloads show that the proposed architecture has an average power saving of 70% over generic register file structure  

This paper presents a new method to counter Anti Radiation Missile (ARM) threats, which is effective against advanced ARM. By using random phase and amplitude active decoys in the specified optimum positions and network implementation we show that ARM threats will be removed profoundly. Also, iterative methods are presented to cancel the internal interference effects in the proposed structure  

This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

There are several key challenges in performing cache-based attacks on ARM-based devices. Lipp et al. introduced various techniques to tackle these challenges and applied successfully different cache-based attacks on ARM-based mobile devices. In the cache-based attacks proposed by Lipp et al. it is assumed that the attacker has access to the mapping of virtual addresses to physical addresses through/proc/self/pagemap which is an important limiting factor in Linux and newer versions of Android operating systems. To access this mapping, the attacker must know the root of the operating system. In this paper, we introduce an Evict+Reload attack on the T-table-based implementation of AES which... 

Microarchitectural attacks utilize the performance optimization constructs that have been studied over decades in computer architecture research and show the vulnerability of such optimizations in a realistic framework. One such highly performance driven vulnerable construct is speculative execution. In this paper, we focus on the problem of breaking the kernel address-space layout randomization (KASLR) on modern mobile devices without using cache memory as a medium of observation. However, there are some challenges to breaking KASLR on ARM CPUs. The first challenge is that eviction strategies on ARM CPUs are slow, and the microarchitectural attacks exploiting the cache as a covert channel... 

Embedded systems are usually energy constrained. Moreover, in these systems, increased productivity and reduced time to market are essential for product success. To design complex embedded systems while reducing the development time and cost, there is a great tendency to use commercial off-the-shelf ("COTS") devices. At system level, dynamic voltage and frequency scaling (DVFS) is one of the most effective techniques for energy reduction. Nonetheless, many widely used COTS processors either do not have DVFS or apply DVFS only to processor cores. In this paper, an easy-to-implement COTS-based evaluation platform for low-energy embedded systems is presented. To achieve energy saving, DVFS is...