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    Efficient hardware implementations of legendre symbol suitable for mpc applications

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; 2021 ; 15498328 (ISSN) Taheri, F ; Bayat Sarmadi, S ; Ebrahimi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture... 

    Efficient hardware implementations of legendre symbol suitable for Mpc applications

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 69, Issue 3 , 2022 , Pages 1231-1239 ; 15498328 (ISSN) Taheri, F ; Bayat Sarmadi, S ; Ebrahimi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    Multi-party computation (MPC) allows each peer to take part in the execution of a common function with their private share of data without the need to expose it to other participants. The Legendre symbol is a pseudo-random function (PRF) that is suitable for MPC protocols due to their efficient evaluation process compared to other symmetric primitives. Recently, Legendre-based PRFs have also been employed in the construction of a post-quantum signature scheme, namely LegRoast. In this paper, we propose, to the best of our knowledge, the first hardware implementations for the Legendre symbol by three approaches: 1) low-area, 2) high-speed, and 3) high-frequency. The high-speed architecture... 

    Analysis, Design and Implementation of a Low Power and High Speed Sound Source Localizer

    , M.Sc. Thesis Sharif University of Technology Zarghi, Hamid Reza (Author) ; Sharif Khani, Mohammad (Supervisor) ; Gholampour, Iman (Supervisor)
    Abstract
    Throughout localization algorithms, sound source localization has received much interest using microphone array. Applications like tracking and determining angle of acoustic signal arrival have been combined with array processing techniques in the previous decade. Distributed micro sensor array have been suggested for a wide range of nowaday’s localization algorithms. The major goals are monitoring the environment, distinction, and pursue some phenomenon. This type of networks can be utilized for military application in tracking acoustic sources. Today’s advancement in technology allows implementation of the ultra low cost and low power integrated circuit for such application in the form of... 

    Design and Implementation of a Multi-Standard Crypto-Processor

    , M.Sc. Thesis Sharif University of Technology Bahadori, Milad (Author) ; Sharif Khani, Mohammad (Supervisor)
    Abstract
    The crypto-processors are used for encryption and decryption of the sensitive and important information. A crypto-processor converts input plaintext to ciphertext by an input key using a particular cryptographic algorithm. It also converts ciphertext to plaintext by the same or another key. Cryptographic standards are divided in two types: symmetric key algorithms (private key) and asymmetric key algorithms (public key). Current processors generally support only one or a few number of cryptographic algorithms. The motivation of this project is design and implementation of a multi-standard crypto-processor which supports the most of symmetric and asymmetric cryptographic algorithms, such as... 

    An Efficient Reconfigurable Architecture Based on Most Frequent Logic Functions

    , M.Sc. Thesis Sharif University of Technology Ahmadpour Yasouri, Iman (Author) ; Asadi, Hossein (Supervisor)
    Abstract
    Reconfigurable devices are a popular platform invarious computational fields due to having high performance and flexibility and low non-recurring engineering cost. Generous flexibility of Look-up Tables (LUTs) in implementing arbitrary functions comes withsignificant area and performance overheads as compared with their Application Specific Integrated Circuit (ASIC) equivalent. One approach to alleviate such overheads is to use less flexible logic elements capable to implement majority of logic functions. In this thesis, we first investigate the most frequently used functions in standard benchmarks and then design a set of less-flexible but area-efficient logic cells, called Hard Logics... 

    Soft error modeling and remediation techniques in ASIC designs

    , Article Microelectronics Journal ; Volume 41, Issue 8 , August , 2010 , Pages 506-522 ; 00262692 (ISSN) Asadi, H ; Tahoori, M. B ; Sharif University of Technology
    2010
    Abstract
    Soft errors due to cosmic radiations are the main reliability threat during lifetime operation of digital systems. Fast and accurate estimation of soft error rate (SER) is essential in obtaining the reliability parameters of a digital system in order to balance reliability, performance, and cost of the system. Previous techniques for SER estimation are mainly based on fault injection and random simulations. In this paper, we present an analytical SER modeling technique for ASIC designs that can significantly reduce SER estimation time while achieving very high accuracy. This technique can be used for both combinational and sequential circuits. We also present an approach to obtain... 

    A compact 8-bit AES crypto-processor

    , Article 2nd International Conference on Computer and Network Technology, ICCNT 2010, 232010 through 25 April 2010 ; April , 2010 , Pages 71-75 ; 9780769540429 (ISBN) Haghighizadeh, F ; Attarzadeh, H ; Sharifkhani, M ; Sharif University of Technology
    2010
    Abstract
    Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standard-cell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far  

    Hardware Acceleration of Convolutional Neural Networks by Computational Prediction

    , M.Sc. Thesis Sharif University of Technology Sajjadi, Pegahsadat (Author) ; Bayatsarmadi, Siavash (Supervisor)
    Abstract
    Recently, Convolutional neural networks (CNNs) are widely used in many artificial intelligence applications such as image processing, speech processing and robotics. The neural networks superior accuracy comes at the cost of high computational complexity. Recent studies show that these operations can be performed in parallel. Therefore, as graphic processing units (GPUs) offer the best performance in terms of computational power and throughput, they are widely used to implement and accelerate neural networks. Nevertheless, the high price and power consumption of these processors have resulted in drawing more attraction towards Field-Programmable Arrays (FPGAs). In order to improve resource... 

    Efficient and concurrent reliable realization of the secure cryptographic SHA-3 algorithm

    , Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Vol. 33, issue. 7 , July , 2014 , p. 1105-1109 ; 0278-0070 Bayat-Sarmadi, S ; Mozaffari-Kermani, M ; Reyhani-Masoleh, A ; Sharif University of Technology
    Abstract
    The secure hash algorithm (SHA)-3 has been selected in 2012 and will be used to provide security to any application which requires hashing, pseudo-random number generation, and integrity checking. This algorithm has been selected based on various benchmarks such as security, performance, and complexity. In this paper, in order to provide reliable architectures for this algorithm, an efficient concurrent error detection scheme for the selected SHA-3 algorithm, i.e., Keccak, is proposed. To the best of our knowledge, effective countermeasures for potential reliability issues in the hardware implementations of this algorithm have not been presented to date. In proposing the error detection... 

    A real-time, low-power implementation for high-resolution eigenvalue-based spectrum sensing

    , Article Analog Integrated Circuits and Signal Processing ; Volume 77, Issue 3 , December , 2013 , Pages 437-447 ; 09251030 (ISSN) Safavi, S. M ; Shabany, M ; Sharif University of Technology
    2013
    Abstract
    In this paper, a novel multiple antenna, high-resolution eigenvalue-based spectrum sensing algorithm based on the FFT of the received signal is introduced. The proposed platform overcomes the SNR wall problem in the conventional energy detection (ED) algorithm, enabling the detection of the weak signals at -10 dB SNR. Moreover, the utilization of FFT for the input signal channelization provides a simple, low-power design for a high-resolution spectrum sensing regime. A real-time, low-area, and low-power VLSI architecture is also developed for the algorithm, which is implemented in a 0.18 μm CMOS technology. The implemented design is the first eigenvalue-based detection (EBD) architecture... 

    High-throughput 0.13-μm CMOS lattice reduction core supporting 880 Mb/s detection

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 21, Issue 5 , July , 2013 , Pages 848-861 ; 10638210 (ISSN) Shabany, M ; Youssef, A ; Gulak, G ; Sharif University of Technology
    2013
    Abstract
    This paper presents the first silicon-proven implementation of a lattice reduction (LR) algorithm, which achieves maximum likelihood diversity. The implementation is based on a novel hardware-optimized due to the Lenstra, Lenstra, and Lovász (LLL) algorithm, which significantly reduces its complexity by replacing all the computationally intensive LLL operations (multiplication, division, and square root) with low-complexity additions and comparisons. The proposed VLSI design utilizes a pipelined architecture that produces an LR-reduced matrix set every 40 cycles, which is a 60% reduction compared to current state-of-the-art LR field-programmable gate array implementations. The 0.13-μm CMOS... 

    A high-throughput VLSI architecture for hard and soft SC-FDMA MIMO detectors

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 62, Issue 3 , January , 2015 , Pages 761-770 ; 15498328 (ISSN) Neshatpour, K ; Shabany, M ; Gulak, G ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    This paper introduces a novel low-complexity multiple-input multiple-output (MIMO) detector tailored for single-carrier frequency division-multiple access (SC-FDMA) systems, suitable for efficient hardware implementations. The proposed detector starts with an initial estimate of the transmitted signal based on a minimum mean square error (MMSE) detector. Subsequently, it recognizes less reliable symbols for which more candidates in the constellation are browsed to improve the initial estimate. An efficient high-throughput VLSI architecture is also introduced achieving a superior performance compared to the conventional MMSE detectors with less than 28% added complexity. The performance of... 

    A 70 pJ/b configurable 64-QAM soft MIMO detector

    , Article Integration ; Volume 63 , 2018 , Pages 74-86 ; 01679260 (ISSN) Shabany, M ; Patel, D ; Milicevic, M ; Mahdavi, M ; Gulak, P. G ; Sharif University of Technology
    Elsevier B.V  2018
    Abstract
    An area and power efficient high-throughput VLSI implementation of a 4 × 4, 64-QAM soft multiple-input-multiple-output (MIMO) detector, that is suitable for high-order constellation schemes is presented. The proposed MIMO detector utilizes information contained in the discarded paths to improve the bit-error-rate (BER) performance, and then reduces computational complexity using three innovative improvement ideas. The proposed design is fabricated and fully tested in a 130 nm CMOS technology. Operating with a 270 MHz clock, the design achieves up to 655 Mbps throughput with 195 mW power dissipation at 1.32 V supply. Synthesis results in 65 nm CMOS technology shows that the proposed...