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ORIENT: organized interleaved ECCs for new STT-MRAM caches
, Article Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 ; Volume 2018-January , 19 April , 2018 , Pages 1187-1190 ; 9783981926316 (ISBN) ; Farbeh, H ; Hosseini Monazzah, A. M ; Sharif University of technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative to SRAM in cache memories. However, STT-MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error-Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT-MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations...