Loading...
Search for:
branch-target-buffers
0.005 seconds
Proposing a Combined BTB and Data Cache Architecture for Modern Processors
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Modern pipelined processors use a memory array named Branch Target Buffer (BTB) to reduce the performance penalty due to conditional braches by predicting path of the branch and keeping useful history-based information for future accesses. Today BTB is a fixed size and small memory array located near the processor. By the way, BTB, in the best case, should be large enough to accommodate all conditional branches throughout the running program. Moreover, small size BTB presents much fast access and is practical on-chip storage for a system with limited power budget.
Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache...
Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache...
Instruction Cache Miss Rate Reduction with Timely Next-Line Prefetching
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
The frontend stalls caused by instruction cache and branch target buffer (BTB) misses are a well-known source of performance degradation in server processors.To address this limitation, a myriad of hardware prefetchers are proposed. While they can effectively eliminate lots of misses and increase performance, they are impractical solutions due to some shortcomings. In this study, we are looking for effective and practical solutions to address these limitations.Since the considerable fraction of instruction cache misses is sequential misses,sequential prefetchers like next-line prefetcher are simple and effective solutions to remove sequential misses that are used in modern server processors....
Power-aware branch target prediction using a new BTB architecture
, Article Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009 ; 2011 , p. 53-58 ; ISBN: 9781457702365 ; Sarbazi-Azad, H ; Zarandi, H. R ; Sharif University of Technology
Abstract
This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using...
Power-aware branch target prediction using a new BTB architecture
, Article Proceedings - 17th IFIP International Conference on Very Large Scale Integration, VLSI-SoC 2009, 12 October 2009 through 14 October 2009 ; October , 2011 , Pages 53-58 ; 9781457702365 (ISBN) ; Sarbazi Azad, H ; Zarandi, H. R ; Sharif University of Technology
2011
Abstract
This paper presents two effective methods to reduce power consumption of branch target buffer (BTB): 1) the first method is based on storing distance to next branch address in tag array instead of storing whole branch address, 2) the second method is to use a new field in data array of BTB namely Next Branch Distance (NBD) which holds distance of next branch address from current branch address. When a new hit is performed in BTB, based on NBD field, there would be no access through NBD number of instructions, so BTB can be shutdown not to consume power. The new architecture does not impose extra delay and reduction in prediction accuracy. Both methods were implemented and simulated using...
Enhancing Branch Target Buffer Efficiency with a Bias-Aware (Re)placement Policy
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor) ; Hessabi, Shaahin (Supervisor)
Abstract
Branch Target Buffer is a widely used component in modern processors. While there are different designs for BTB, they generally have a set-associative structure keeping branches and their target to help the frontend fetch the instructions on the correct path. To achieve high performance, it’s essential to obtain a high hit rate out of the BTB. Prior works has shown that BTB suffers from frequent misses that require large sizes or sophisticated BTB prefilling mechanisms to overcome the problem. However, the first solution imposes a significant storage overhead, and the latter results in limited benefits. Prior works have shown that branches exhibit different behaviors from being strongly...