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The effect of virtual channel organization on the performance of interconnection networks
, Article 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, Denver, CO, 4 April 2005 through 8 April 2005 ; Volume 2005 , 2005 ; 0769523129 (ISBN); 0769523129 (ISBN); 9780769523125 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
2005
Abstract
Most of previous studies have assessed the performance issues for regular buffer and virtual channel organiza-tions and have not considered overall buffer size constraint. In this paper, the performance of mesh-based interconnection networks (mesh, torus and hypercube networks) under different traffic patterns (uniform, hotspot, and matrix-transpose) is studied. We investigate the effect of the number of virtual channels and their buffer lengths, on the performance of these topologies when the total buffer size associated to each physical channel (and thus router buffer size) is fixed.The results show that the optimal number of virtual channels and buffer length highly depends on the traffic...
New approach to VLSI buffer modeling, considering overshooting effect
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 21, Issue 8 , August , 2013 , Pages 1568-1572 ; 10638210 (ISSN) ; Kouhani, M. H. M ; Masoumi, N ; Sarvari, R ; Sharif University of Technology
2013
Abstract
In this brief, we use the alpha power law model for MOS devices to reach a more accurate modeling of CMOS buffers in very deep submicrometer technologies. We derive alpha model parameters of a CMOS buffer for 90-, 65-, and 45-nm technologies using HSPICE simulations. By analytical efforts we find the output resistance of a minimum-size buffer and compare it with those extracted from HSPICE simulations. We propose a new model for the output resistance of a given-size buffer in any technology, which demonstrates 3% error on average as opposed to the conventional model. Also a new buffer resistance is proposed analytically and numerically to calculate the crosstalk for interconnect analysis...
Jitter-buffer management for VoIP over wireless LAN in a limited resource device
, Article 4th International Conference on Networking and Services, ICNS 2008, Gosier, 16 March 2008 through 21 March 2008 ; 2008 , Pages 90-95 ; 076953094X (ISBN); 9780769530949 (ISBN) ; Tabandeh, M ; Behboodi, A ; Fotowat Ahmadi, A ; Sharif University of Technology
2008
Abstract
VoIP over WLAN is a promising technology as a powerful replacement for current local wireless telephony systems. Packet timing Jitter is a constant issue in QoS of IEEE802.11 networks and exploiting an optimum jitter handling algorithm is an essential part of any VoIP over WLAN (VoWiFi) devices especially for the low cost devices with limited resources. In this paper two common algorithms using buffer as a method for Jitter handling are analyzed with relation to different traffic patterns. The effect of different buffer sizes on the quality of voice will be assessed for these patterns. Various traffic patterns were generated using OPNET and Quality of output voice was evaluated based on ITU...
Project buffer sizing and dynamic buffer consumption algorithm in power generation construction
, Article Engineering, Construction and Architectural Management ; Volume 29, Issue 2 , 2022 , Pages 716-738 ; 09699988 (ISSN) ; Khalilzadeh, M ; Amiri, M ; Shadrokh, S ; Sharif University of Technology
Emerald Group Holdings Ltd
2022
Abstract
Purpose: The aim of this research is to propose a buffer sizing and buffer controlling algorithm (BSCA) as a heuristic algorithm for calculating project buffer and feeding buffers as well as dynamic controlling of buffer consumption in different phases of a wind power plant project in order to achieve a more realistic project duration. Design/methodology/approach: The BSCA algorithm has two main phases of planning and buffer sizing and construction and buffer consumption. Project buffer and feeding buffers are determined in the planning and buffer sizing phase, and their consumption is controlled in the construction and buffer consumption phase. The heuristic algorithm was coded and run in...
A fuzzy project buffer management algorithm: a case study in the construction of a renewable project
, Article International Journal of Construction Management ; 2022 ; 15623599 (ISSN) ; Vanhoucke, M ; Khalilzadeh, M ; Amiri, M ; Shadrokh, S ; Sharif University of Technology
Taylor and Francis Ltd
2022
Abstract
One of the major problems with projects is that they are not completed according to schedule. Uncertainty always exists at the heart of real-world project scheduling problems. This paper introduces a fuzzy project buffer management (FPBM) algorithm which is a combination of the adaptive procedure with resource tightness (APRT) and fuzzy failure mode and effects analysis (FFMEA) methods. This paper aims to present an efficient model for project buffer sizing by taking FFMEA into account to reach a more realistic schedule. In this research, for increasing the efficiency of the APRT method, the FFMEA technique is simultaneously applied with them. This research was carried out as a case study in...
Proposing a Combined BTB and Data Cache Architecture for Modern Processors
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
Modern pipelined processors use a memory array named Branch Target Buffer (BTB) to reduce the performance penalty due to conditional braches by predicting path of the branch and keeping useful history-based information for future accesses. Today BTB is a fixed size and small memory array located near the processor. By the way, BTB, in the best case, should be large enough to accommodate all conditional branches throughout the running program. Moreover, small size BTB presents much fast access and is practical on-chip storage for a system with limited power budget.
Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache...
Considering role in the memory hierarchy, on the other hand, the system performance is highly correlated to the L1 data cache...
Instruction Cache Miss Rate Reduction with Timely Next-Line Prefetching
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
The frontend stalls caused by instruction cache and branch target buffer (BTB) misses are a well-known source of performance degradation in server processors.To address this limitation, a myriad of hardware prefetchers are proposed. While they can effectively eliminate lots of misses and increase performance, they are impractical solutions due to some shortcomings. In this study, we are looking for effective and practical solutions to address these limitations.Since the considerable fraction of instruction cache misses is sequential misses,sequential prefetchers like next-line prefetcher are simple and effective solutions to remove sequential misses that are used in modern server processors....
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Vol. 29, issue. 10 , 2010 , p. 1558-1571 ; ISSN: 02780070 ; Sarbazi-Azad, H ; Sharif University of Technology
Abstract
End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual...
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 29, Issue 10 , September , 2010 , Pages 1558-1571 ; 02780070 (ISSN) ; Sarbazi Azad, H ; Sharif University of Technology
2010
Abstract
End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual...
Investigation of CeO2 buffer layer effects on the voltage response of YBCO transition-edge bolometers
, Article IEEE Transactions on Applied Superconductivity ; Volume 26, Issue 3 , 2016 ; 10518223 (ISSN) ; Nazifi, R ; Wulff, A. C ; Vesaghi, M. A ; Grivel, J. C ; Fardmanesh, M ; Sharif University of Technology
Abstract
The effect on the thermal parameters of superconducting transition-edge bolometers produced on a single crystalline SrTiO3 (STO) substrate with and without a CeO2 buffer layer was investigated. Metal-organic deposition was used to deposit the 20-nm CeO2 buffer layer, whereas RF magnetron sputtering was applied to fabricate 150-nm-thick superconducting YBa2Cu3O7-δ (YBCO) thin film. The critical transition temperature for both of the YBCO films was 90 K, and the transition width was ∼1.9 K. The bolometers fabricated from these samples were characterized with respect to the voltage phase and amplitude responses, and the results were compared with that of simulations conducted by applying a...
Fabrication and Characterization of the Buffer Layer and Interface with Absorbent Layer in Chalcopyrite Solar Cells Thin Layers by Solubility-Based Methods
, M.Sc. Thesis Sharif University of Technology ; Taghavinia, Nima (Supervisor) ; Dehghani, Mehdi (Supervisor)
Abstract
In this research, the first attempt was made to increase the thickness of the absorbent layer and increase the size of the absorbent layer crystals and minimize the cavities of this layer. this attempt resulted in the synthesis of absorbent layer with a thickness of about one micrometer and with low cavities. then, an attempt was made to crystallize the buffer layer and form the bond with the absorbent layer. these efforts led to the synthesis of a cadmium sulfide layer with a high carrier density. in this study, cadmium sulfide and cadmium zinc sulfide and indium sulfide were used to make the cell. then we could synthesizing window layer with low resistance.at end, we made superstrate...
A fault-tolerant cache architecture based on binary set partitioning
, Article Microelectronics Reliability ; Volume 46, Issue 1 , 2006 , Pages 86-99 ; 00262714 (ISSN) ; Miremadi, S. G ; Sharif University of Technology
2006
Abstract
Caches, which are comprised much of a CPU chip area and transistor counts, are reasonable targets for transient single and multiple faults induced from energetic particles. This paper presents: (1) a new fault detection scheme for tag arrays of cache memories and (2) an architectural cache to improve performance as well as dependability. In this architecture, cache space is divided into sets of different sizes and different tag lengths. Using the proposed fault detection scheme, i.e., GParity, when single and multiple errors are detected in a word, the word is rewritten by its correct data from memory and its GParity code is recomputed. The error detection scheme and the cache architecture...
Hierarchical set-associate cache for high-performance and low-energy architecture
, Article Journal of Circuits, Systems and Computers ; Volume 15, Issue 6 , 2006 , Pages 861-880 ; 02181266 (ISSN) ; Miremadi, G ; Sharif University of Technology
2006
Abstract
This paper presents a new cache scheme based on varying the size of sets in the set-associative cache hierarchically. In this scheme, all sets at a hierarchical level have same size but are fc times more than the size of sets in the next level of hierarchy where k is called division factor. Therefore the size of tag fields associated to each set is variable and it depends on the hierarchy level of the set it is in. This scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. The proposed scheme has been simulated with several standard trace files SPEC 2000 and statistics are gathered and analyzed for different...
Hierarchical multiple associative mapping in cache memories
, Article Proceedings - 12th IEEE International Conference and Workshops on the Engineering of Computer-Based Systems, ECS 2005, Greenbelt, MD, 4 April 2005 through 7 April 2005 ; 2005 , Pages 95-101 ; 0769523080 (ISBN); 9780769523088 (ISBN) ; Miremadi, S. G ; Rozenblit J ; O'Neill T ; Peng J ; Sharif University of Technology
2005
Abstract
In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of different sizes. Hence, the length of tag fields associated to each set is also variable and depends on the partition it is in. The proposed mapping function has been simulated with some standard trace files and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping,...
Hierarchical binary set partitioning in cache memories
, Article Journal of Supercomputing ; Volume 31, Issue 2 , 2005 , Pages 185-202 ; 09208542 (ISSN) ; Sarbazi Azad, H ; Sharif University of Technology
2005
Abstract
In this paper, a new cache placement scheme is proposed to achieve higher hit ratios with respect to the two conventional schemes namely set-associative and direct mapping. Similar to set-associative, in this scheme, cache space is divided into sets of different sizes. Hence, the length of tag fields associated to each set is also variable and depends on the partition it is in. The proposed mapping function has been simulated with some standard trace files and statistics are gathered and analyzed for different cache configurations. The results reveal that the proposed scheme exhibits a higher hit ratio compared to the two well-known mapping schemes, namely set-associative and direct mapping,...
MOD growth of epitaxial cerium oxide buffer layer on LAO substrates for fabrication of c-axis oriented YBCO
, Article Micro and Nano Letters ; Volume 7, Issue 10 , 2012 , Pages 1008-1010 ; 17500443 (ISSN) ; Foroughi Abari, F ; Vesaghi, M. A ; Fardmanesh, M ; Sharif University of Technology
2012
Abstract
Epitaxial cerium oxide (CeO2) buffer layer has been grown on lanthanum aluminate (LAO) single crystal substrates for fabrication of c-axis oriented YBa2Cu3O7-x (YBCO). Precursor solution of cerium acetylacetonates with viscosity of 0.6 centipoises was spin coated on the 1×1 cm area LAO substrates. The calcination was carried out by very slow ramp (1°C per minute) until the final temperature of 500°C in oxygen flow to remove most of the organic compounds. The final heat treatment has been done at 780°C by a ramp of 20° per minute in gas flow of mixed argon-oxygen with 5 Pa partial pressure of oxygen. The thickness of the deposited CeO2 buffer layer was 20 nm. Then, 100 nm thick YBCO film was...
Virtual optical buffers: A novel interpretation of OCDMA in packet switch networks
, Article Journal of Lightwave Technology ; Volume 30, Issue 18 , July , 2012 , Pages 2964-2975 ; 07338724 (ISSN) ; Rashidinejad, A ; Nashtaali, D ; Salehi, J. A ; Sharif University of Technology
IEEE
2012
Abstract
Among all proposed structures for optical networks, the optical packet switching (OPS) scheme, due to its practical implementation of IPs in an optical configuration and the consequent advantages, is a prizeworthy candidate for being employed in metropolitan area network and local area network communication levels. One of the few problems frequently met using the OPS structure in the fiber-optics realm is the lack of optical buffers, thus deteriorating the system's flexibility and quality of service. For example, optical label switching networks that have been developed recently based on the generalized multiprotocol label switching protocol, profoundly suffer from this setback which is...
Modeling of a glucose sensitive composite membrane for closed-loop insulin delivery
, Article Journal of Membrane Science ; Volume 335, Issue 1-2 , 2009 , Pages 21-31 ; 03767388 (ISSN) ; Wu, X. Y ; Sharif University of Technology
2009
Abstract
A theoretical model was developed to describe a dynamic process involving an enzymatic reaction and diffusion of reactants and product inside glucose sensitive composite membrane. The composite membrane consisted of nanoparticles of a weakly acidic polymer, glucose oxidase and catalase embedded in a hydrophobic polymer. Time- and position-dependent diffusivity of involved species was considered in the model. Donnan equilibrium was used to find concentrations of buffer ions inside the membrane. The profiles of pH, species concentrations, volume fraction of swollen gel, polymer and water-filled space, as well as solute diffusivity inside the membrane were predicted by the model as a function...
Multi-Objective Simulation Optimization and its Application in Buffer Allocation Problem
,
M.Sc. Thesis
Sharif University of Technology
;
Mahlooji, Hashem
(Supervisor)
Abstract
This work attempts to address the buffer allocation problem in an unreliable, linear production line. We try to determine the optimal sizes of buffers between adjacent work stations in such a way that a measure of costs is minimized and the production rate is simultaneously maximized. We resort to simulation optimization in order to determine the best combination of input parameters that leads to a near optimal performance for the system. To achieve this purpose, we employ a multi-objective genetic algorithm (NSGAII) in the optimization phase along with simulation as the tool for evaluating the objective function. To determine the merits of the proposed method, we compare the performance of...
Buffer Modeling and Optimization for NSoLT (Near Speed of Light Transmission)in Future Technologies
, M.Sc. Thesis Sharif University of Technology ; Sarvari, Reza (Supervisor)
Abstract
As the transistors’ dimensions in integrated circuits shrink, according to Moore’s law, a number of challenges emerges that can decrease the benefits of scaling. One of the main challenges in deep submicron CMOS technologies is the delay in interconnects. In recent years, researchers have been looking into different methods to minimize the delay in interconnects. International Technology Roadmap for Semiconductors (ITRS) predicts that the input capacitance of a buffer will become in the order of 10s of aFs with technology scaling. This will give us the opportunity to transmit the data in electrical interconnects near the speed of light.In this thesis, a novel buffer is designed in which the...