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Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Vol. 29, issue. 10 , 2010 , p. 1558-1571 ; ISSN: 02780070 ; Sarbazi-Azad, H ; Sharif University of Technology
Abstract
End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual...
Power-performance analysis of networks-on-chip with arbitrary buffer allocation schemes
, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 29, Issue 10 , September , 2010 , Pages 1558-1571 ; 02780070 (ISSN) ; Sarbazi Azad, H ; Sharif University of Technology
2010
Abstract
End-to-end delay, throughput, energy consumption, and silicon area are the most important design metrics of networks-on-chip (NoCs). Although several analytical models have been previously proposed for predicting such metrics in NoCs, very few of them consider the effect of message waiting time in the buffers of network routers for predicting overall power consumptions and none of them consider structural heterogeneity of network routers. This paper introduces two inter-related analytical models to compute message latency and power consumption of NoCs with arbitrary topology, buffering structure, and routing algorithm. Buffer allocation scheme defines the buffering space for each individual...