Sharif Digital Repository

In this paper we present a new fault model for testing bus components using their functionality. With the aim of a new fault model definition all components in a bus except cores of the SoC will be tested as fast as possible. According to the proposed method in this paper, at first, wires and small components will be tested by marching test patterns as the test data and, after that based on a proposed method; the new format faults for the bus will be used. Using AMBA-AHB as the experimental result, the new fault model shows efficiency in comparison with corresponding stuck-at  

In this paper we present a new fault model for testing standard On-Chip buses using a graph model. This method will be optimized for speed of testing. Using AMBA-AHB as the experimental result, the proposed fault model shows efficiency in comparison with corresponding stuck-At fault testing  

This paper presents an analysis of the effects and propagation of faults in the open-core 32-bit OpenRISC 1200 microprocessor. The analysis is based on a total of 13,000 transient faults injected into 65 parts of the CPU module in the OpenRISC 1200 core described at the RTL model. A comparison of the effects of faults on the various parts of the CPU including the pipeline's registers, the CPU component such as the register file, the control unit, and the ALU, and the data and address buses is done. It is shown that about 30%, 40% and 27% of injected faults terminated in address, data, and control errors respectively. About 28% of all injected faults resulted in failures. © 2008 IEEE  

Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. So far, many techniques have been proposed for reducing the self and coupling powers. Most of these methods utilize one (or more) control bit(s) to manage the behavior of data transitions on the parallel bus. In this paper, we propose a new coding scheme, referred to as GPH, to reduce power dissipation of these control bits. GPH coding scheme employs partitioned Bus Invert and Odd Even Bus-Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce self and coupling powers of... 

Two main sources for power dissipation in parallel buses are data transitions on each wire and coupling between adjacent wires. There are many techniques for reducing the transition and coupling powers. These methods utilize extra control bits to manage the behavior of data transitions on parallel bus. In this paper, we propose a new coding scheme which tries to reduce power dissipation of control bits. The proposed method employs partitioned Bus Invert and Odd Even Bus Invert coding techniques. This method benefits from Particle Swarm Optimization (PSO) algorithm to efficiently partition the bus. In order to reduce transition and coupling power of control bits, it finds partitions with... 

This paper investigates fault effects and error propagation in a FlexRay-based network with hybrid topology that includes a bus subnetwork and a star subnetwork "The investigation is based on about 43500 bit-flip fault injection inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of eight nodes (four nodes in the bus subnetwork and four nodes in the star subnetwork). The faults are injected in a node of the bus subnetwork and a node of the star subnetwork of the hybrid network. Then, the faults resulting in... 

This paper evaluates the error propagation and its effects in babbling idiot failure in a FlexRay-based network. The evaluation is based on about 35680 bit-flip fault injections inside different parts of the FlexRay communication controller. To do this, a FlexRay communication controller is modeled by Verilog HDL at the behavioral level. Then, this controller is exploited to setup a FlexRay-based network composed of four nodes. Nodes in this experiment are considered in two forms: 1) node without bus guardian, 2) node with bus guardian. The results of fault injection show that in first form about 4.57% of faults lead to the babbling idiot failures. Also in second form about 0.75% faults lead... 

Reactive power compensation is known as an effective tool to overcome the violations of voltage limits in electric power systems. It is also deployed to be an efficient method to minimise transmission losses. In order to maximize the effectiveness of reactive power compensation, VAr sources of proper sizes should be placed at some network buses. In this paper, a new VAr expansion tool has been developed to improve the voltage profile and reduce MW losses in a bulk power network. Keeping the minimum expansion cost and minimum switching of capacitor banks during change of load level of the system are emphasized in the proposed method. This method is based on application of genetic algorithm in... 

Low scalability and power efficiency of the shared bus in SoCs is a motivation to use on chip networks instead of traditional buses. In this paper we have modified the Orion power model to reach an analytical model to estimate the average message energy in K-Ary n-Cubes with focus on the number of virtual channels. Afterward by using the power model and also the performance model proposed in [11] the effect of number of virtual channels on Energy-Delay product have been analyzed. In addition a cycle accurate power and performance simulator have been implemented in VHDL to verify the results. ©2008 IEEE  

Of particular interest to restrict the short-circuit level of interconnected power systems is to exploit fault current limiter (FCL) technologies. FCLs let the system planners devise new reliable and rather economical substation configurations and provide the possibility of proposing a promising cost-effective and prompt solution to the fault current over duty problem in the existing substations. This paper attempts to assess reliability of substation architectures accommodating the FCL operation and, besides, numerically investigates the FCL's impacts on the substation reliability indices. In order to clarify the proposed approach, two case studies with and without FCL are analyzed and... 

The bus network design problem is an important problem in transportation planning. It is the problem of determining a network of bus lines which best achieves a predetermined objective. This may be done with or without the presence of rapid transit lines. This study is devoted to solving this problem using genetic algorithm. The fitness function is defined as the benefit to the users of the bus network less the cost of the operator of the network, which is to be maximized subject to constraints that properly distribute bus routes over the study area. Objective function calculation depends on the basic data of the city and its bus lines and does not need traffic assignment results. So, it is... 

Of particular interest to restrict the short-circuit level of interconnected power systems is to exploit fault current limiter (FCL) technologies. FCLs let the system planners devise new reliable and rather economical substation configurations and provide the possibility of proposing a promising cost-effective and prompt solution to the fault current over duty problem in the existing substations. This paper attempts to assess reliability of substation architectures accommodating the FCL operation and, besides, numerically investigates the FCL's impacts on the substation reliability indices. In order to clarify the proposed approach, two case studies with and without FCL are analyzed and... 

A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement  

We propose modified hybridizations of genetic algorithms with some neighborhood search based metaheuristics. In our hybrid algorithms, we consider gradually increasing probability for the application of the neighborhood search procedure on the best individuals as the number of iterations of the genetic algorithm increases. We implement the proposed hybrid algorithms and compare their performance with two other recently proposed hybrid algorithms which, in contrast, use the neighborhood search procedure on all the individuals of the population, two hybrid algorithms applying simulated annealing on the best individual in the papulation in every iteration and three non-hybrid metaheuristic... 

Polymorphism and dynamic binding of processing units to methods are key features in object-oriented (OO) processors. Since Network-on-Chip is not available for most platform implementation, common bus can be a good approach to interconnect processing units of an OO processor. In this paper, we present a network protocol with little overhead for common bus that does not violate the polymorphism method calls in an OO processor. Moreover, we show the appropriateness of our solution by presenting a real-world application. © 2008 Springer-Verlag  

Appearances of specific transition patterns during data transfer in bus lines of modern high-performance computing systems, such as communicating structures of accelerators for deep convolutional neural networks, commercial Network on Chips, and memories, can lead to crosstalk faults. With the shrinkage of technology size, crosstalk faults occurrence boosts and leads to degradation of reliability and performance, as well as the increasing power consumption of lines. One effective way to alleviate crosstalk faults is to avoid the appearance of these specific transition patterns by using numerical-based crosstalk avoidance codes (CACs). However, a serious problem with numerical-based CACs is... 

In this paper, a new software is introduced that is developed to give the most appropriate solution for the component selection and design of a hybrid electric bus. There are several simulation programs that can simulate behavior of a hybrid electric bus, but most of them are not able to suggest the best design and the best choice of the components. Customer requirements are dissimilar and there are several different parameters that they may need. Cost, pollution, driving cycle, battery type, DC link voltage, weight, volume, fuel consumption, and acceleration are some parameters that vary from one customer to the other. The stated software that is developed and presented by this paper will... 

This paper presents an optimization model for the calculation of the minimum number of phasor measurement units (PMUs) in electrical power networks. The problem constraint is a predefined probability of observability associated with each bus. The mixed-integer programming is used for the proposed optimization and an efficient linearization technique is proposed to convert the nonlinear function representing the probability of observability into a set of linear expressions. The PMU placement is staged in a multi-year planning horizon due to financial and physical constraints. The average probability of observability is maximized at the intermediate planning stages, subject to a limited number... 

This paper enhances the observability of power networks by taking into consideration random component outages. The architecture of wide-area measurement system (WAMS) is analyzed in order to identify components that would affect the network observability. An iterative framework is devised to calculate a bus index in power networks equipped with phasor measurement units (PMUs) and conventional measurements. The average of bus indices represents a system index which provides an overall insight on the power network observability. The system index is utilized as a criterion to distinguish among multiple optimal PMU placements. Conventional bus injection and line flow measurements and the effect...