Sharif Digital Repository

According to Moor’s law, the number of transistors per chip would double every 1.5 years. It means that the number of processors, memory and hardware cores available on the chip also increases. In SoC, a number of IP cores and communication links or buses are integrated on a chip. According to inefficiency of the interconnection bus used in SoCs for a large number of processors, NoC has been introduced in the beginning of the current decade. In the NoC paradigm a router-based network is used for packet switched on-chip communication among cores. A typical NoC architecture will provide a scalable communication infrastructure for interconnecting cores. One of the most important features of... 

Due to the increasing need of use of drugs and insufficient efficiency of conventional methods, drug delivery systems has gathered a lot of interests. There are different systems existing for controlled drug delivery, among which is implementation of hydrogel microparticles (microgels) as carriers with high potential. The most important factor in these systems is size distribution of drug-carrying microgels and a narrow size distribution leads to a controlled and suitable release. Due to unique characteristics of microfluidic systems, significant focus has been placed on them nowadays for production of microgels with suitable morphology and narrow size distribution. Therefore, in this study... 

Networks on Chip have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of IP cores (or processing elements) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of chips. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs on to the tiles of the network. Different mapping algorithms have been proposed for Network on Chips which allocate a set of Intellectual Properties (IPs) to determined network topologies. In these mapping... 

With progress in integrated circuits technology, on chip systems have become operational, and after that, onchip network are as solutions to improve onchip connections and also its scalability. With improving technology, the number of cores on chips can be more, that it causes increasing importance of produced problems by parallel links. Serial links are one of the methods to decrease these problems. Serial links have some advantages in compare with parallel links in some aspects like: clock pulse skew, cross talk, area cost, difficulties in wiring and synchronizing clock pulse signals. But any way, problems such as high operational frequency and complicated serializer and deserializer... 

Use of nano-scale VLSI technologies in the fabrication of System-on-Chips (SoCs) makes reliability as one of the major issues in the design and implementation of these products. SoCs are susceptible to several fault sources such as crosstalks, cosmic particle strikes, electromagnetic interferences, and power supply disturbances. Among the mentioned fault sources, crosstalks have the major contribution in threatening the reliability of SoCs. This thesis addresses the modeling and mitigation of crosstalk faults. In this regard, two analytical models and three crosstalk reduction methods have been introduced. The proposed analytical models, which have been introduced in the fourth chapter of... 

Heterogeneity is one of the challenges in the current NoC (Network-on-Chip) domain which oblige designers to consider less regular topologies to provide the best cost-performance trade-off while minimizing resource and power consumption and providing the maximum flexibility. Irregular mesh is a topology which combines the benefits of regularity and advantage of irregularity. Another important issue in any NoC is the selection of routing algorithm which provides the best performance. Routing algorithms especially those coupled with wormhole switching should deal with deadlock occurrences. Deadlock detection and recovery-based routing schemes for this type of switching gained attraction since... 

From the cache of the personal computers to the main memory unit of SOCs, medical and wearable chips, Static Random Access Memory (SRAM) is widely utilizes. Preferable performance for SRAM varies with regard to the operating field. For instance, high speed access and performance is emphasized in the design of the cache for PCs. In contrast, power consumption and the area of the memory are the key design considerations for SOCs. Hence, the field in which SRAM is used, should be thoroughly studied. SOCs and medical chips suffer limitations in design due to using batteries as the source of energy and SRAMs consume a significant part of total power and occupy a large area on these chips. One of... 

It is now possible to integrate hundreds of modules (e.g. processors, memories) in a single silicon die. Handling the communication requirements between such modules by interconnecting them using shared buses is not possible from the performance point of view. One of the solutions is to use a network-on-chip (NoC) based communication infrastructure. NoCs were shown to be effective for solving the global interconnection problem among modules. These architectures emphasize the separation between computing and communication, and guarantee a good degree of design reuse and scalability. Mesh topology is favored by many researchers as the topology of NoCs because of its layout efficiency....