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Power and performance efficient partial circuits in packet-switched networks-on-chip
, Article Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013 ; 27 February - 1 March , 2013 , pp. 509-513 ; Print ISBN: 9781467353212 ; Modarressi, M ; Sarbazi-Azad, H ; Sharif University of Technology
Abstract
In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs...
Power and performance efficient partial circuits in packet-switched networks-on-chip
, Article Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2013 ; February , 2013 , Pages 509-513 ; 9780769549392 (ISBN) ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
2013
Abstract
In this paper, we propose a hybrid packet-circuit switching for networks-on-chip to benefit from the advantages of both switching mechanisms. Integrating circuit and packet switching into a single NoC is achieved by partitioning the link bandwidth and router data-path and control-path elements into two parts and allocating each part to one of the switching methods. In this NoC, during injection in the source node, packets are initially forwarded on the packet-switched sub-network, but keep requesting a circuit towards the destination node. The circuit-switched part, at each cycle, collects the circuit construction requests, performs arbitration among the conflicting requests, and constructs...
Performance and power efficient on-chip communication using adaptive virtual point-to-point connections
, Article 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009, San Diego, CA, 10 May 2009 through 13 May 2009 ; 2009 , Pages 203-212 ; 9781424441433 (ISBN) ; Sarbazi Azad, H ; Tavakkol, A ; IEEE Circuits and Systems Society; Council for EDA; ACM Special Interest Group on Computer Architecture (SIGARCH); ACM Special Interest Group on Embedded Systems (SIGBED); ACM Special Interest Group on Design Automation (SIGDA); Silistix, Inc ; Sharif University of Technology
2009
Abstract
In this paper, we propose a packet-switched network-on-chip (NoC) architecture which can provide a number of low-power, low-latency virtual point-to-point connections for communication flows. The work aims to improve the power and performance metrics of packet-switched NoC architectures and benefits from the power and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The virtual point-to-point connections are set up by bypassing the entire router pipeline stages of the intermediate nodes. This work addresses constructing the virtual point-to-point connections at run-time using a light-weight setup network. It involves monitoring...