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Step response analysis of third order OpAmps with slew-rate
, Article IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC ; 2013 , Pages 62-63 ; 23248432 (ISSN); 9781479905249 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
IEEE Computer Society
2013
Abstract
Drawing an accurate relationship between settling time and the power consumption of the amplifier is a challenging problem in Switch Capacitor circuits especially when it includes non-linear effects. In this paper, a new method for the estimation of this relationship including both non-linear settling as a result of slew-rate and small signal settling in the 3 rd order amplifier is proposed. The results show that the proposed settling time estimation is more accurate than other conventional methods when it is compared with the circuit level simulations. The proposed method has error smaller than 10% for the third order OpAmp in estimating settling error. This is about two times more accurate...
Analysis of integral non-linearity errors in two-step analogue-to-digital converters
, Article IET Circuits, Devices and Systems ; Volume 6, Issue 1 , January , 2012 , Pages 1-8 ; 1751858X (ISSN) ; Medi, A ; Sharif University of Technology
Abstract
A new method for modelling and analysis of non-linearity errors caused by the capacitor mismatches and op-amp non-idealities in two-step analogue-to-digital converters (ADCs) is presented. Analytical formulas for estimation of the ADC integral non-linearity (INL) are derived. Using the proposed method, the ADC INL can be calculated in terms of the capacitor mismatches standard deviations. Therefore time-consuming Monte Carlo simulations which are conventionally used to evaluate the effect of random capacitor mismatches on the ADC linearity can be avoided. The effect of op-amp non-idealities, which are frequently examined by the circuit-level simulations, can also be evaluated using the...
A compact hybrid current/voltage sense amplifier with offset cancellation for high-speed SRAMs
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 19, Issue 5 , 2011 , Pages 883-894 ; 10638210 (ISSN) ; Rahiminejad, E ; Jahinuzzaman, S. M ; Sachdev, M ; Sharif University of Technology
Abstract
A hybrid current/voltage sense amplification scheme is proposed for high speed SRAMs. The scheme includes an offset cancellation technique which makes it robust against the current sense amplifier (CSA) mismatch. The offset cancellation allows for fast open loop operation of the differential CSA. A fourfold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. Thanks to its automatic turn off nature, the proposed CSA incurs zero static power without an auxiliary turn off circuit. The reduction of the charge redistribution on the bitlines offers a low bitline dynamic power consumption as well. In this work, the...