Sharif Digital Repository

Drawing an accurate relationship between settling time and the power consumption of the amplifier is a challenging problem in Switch Capacitor circuits especially when it includes non-linear effects. In this paper, a new method for the estimation of this relationship including both non-linear settling as a result of slew-rate and small signal settling in the 3 rd order amplifier is proposed. The results show that the proposed settling time estimation is more accurate than other conventional methods when it is compared with the circuit level simulations. The proposed method has error smaller than 10% for the third order OpAmp in estimating settling error. This is about two times more accurate... 

New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in class-AB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18μm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method  

A new method for modelling and analysis of non-linearity errors caused by the capacitor mismatches and op-amp non-idealities in two-step analogue-to-digital converters (ADCs) is presented. Analytical formulas for estimation of the ADC integral non-linearity (INL) are derived. Using the proposed method, the ADC INL can be calculated in terms of the capacitor mismatches standard deviations. Therefore time-consuming Monte Carlo simulations which are conventionally used to evaluate the effect of random capacitor mismatches on the ADC linearity can be avoided. The effect of op-amp non-idealities, which are frequently examined by the circuit-level simulations, can also be evaluated using the... 

This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition  

A hybrid current/voltage sense amplification scheme is proposed for high speed SRAMs. The scheme includes an offset cancellation technique which makes it robust against the current sense amplifier (CSA) mismatch. The offset cancellation allows for fast open loop operation of the differential CSA. A fourfold reduction of the cell access time is achieved compared to the conventional scheme under similar cell current and bitline capacitance. Thanks to its automatic turn off nature, the proposed CSA incurs zero static power without an auxiliary turn off circuit. The reduction of the charge redistribution on the bitlines offers a low bitline dynamic power consumption as well. In this work, the... 

A novel sturdy multi-stage noise-shaping sigma-delta modulator that cancels the first-stage quantisation error at the output of the modulator is presented. Since any stage of the modulator has unity signal transfer function, the modulator would be very robust to circuit non-idealities such as finite op-amp gain. Furthermore, the signal processing timing issue in the critical paths of the proposed topology has been relaxed due to shifting the delay of the last integrator to the feedback path of the modulator. Moreover, this topology can be implemented in the circuit level by a fewer active blocks. Therefore, it practically would be suitable for low-voltage and low-oversampling applications.... 

A low power 10 bit, 40 MS/s pipeline analog to digital converter is presented. A number of low-power techniques are proposed in various levels of abstraction. In circuit level, a low power class A/AB opamp with direct common-mode-feedback circuit (CMFB) is proposed which significantly reduces power in the opamps. In backend design, optimal series capacitors are layed out to break the deadlock between the mismatch and loading effect of the first stage capacitors. A customized software tool is developed based on the proposed opamp and architecture which provides optimum stage scaling factors, tail current and opamp transistor sizes. Simulations in 0.13um CMOS technology show that the ADC... 

This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise and jitter. To cover the desired frequency proposed architecture consists of mixer and divider. As an example, VHF frequency band of IRAN is covered. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a 40 delay cell and 9 switches for switching channels is sufficient. Simulation results confirm the analytical predictions  

This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions  

Nanoelectromechanical (NEM) relays are a promising emerging technology that has gained widespread research attention due to its zero leakage current, sharp ON-OFF transitions, and complementary metal-oxide-semiconductor compatibility. As a result, NEM relays have been significantly investigated as highly energy-efficient design solutions. A major shortcoming of NEMs preventing their widespread use is their limited switching endurance. Hence, in order to utilize the low-power advantages of NEM relays, further device, circuit, and architectural techniques are required. In this paper, we introduce the concept of shadow NEM relays, which is a circuit-level technique to leverage the energy... 

This paper presents a circuit level soft error-tolerant-technique, called RRC (Robust Register Caching), for the register file of embedded processors. The basic idea behind the RRC is to effectively cache the most vulnerable registers in a small highly robust register cache built by circuit level SEU and SET protected memory cells. To decide which cache entry should be replaced, the average number of read operations during a register ACE time is used as a criterion to judge. In fact, the victim cache entry is one which has the maximum read count. To minimize the power overhead of the RRC, the clock gating technique is efficiently exploited for the main register file resulting in...