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    Topological properties of stretched graphs

    , Article IEEE International Conference on Computer Systems and Applications, 2006, Sharjah, 8 March 2006 through 8 March 2006 ; Volume 2006 , 2006 , Pages 647-650 ; 1424402123 (ISBN); 9781424402120 (ISBN) Shareghi, P ; Sarbazi Azad, H ; Sharif University of Technology
    IEEE Computer Society  2006
    Abstract
    We study a class of interconnection networks for multiprocessors, called the Stretched-G network, which is based on the base graph G by replacing each edge of the base network with an array of processors. Two interesting features of the proposed topology are its area-efficient VLSI layout and superior scalability over the underlying base network while preserving most of its desirable properties. We conduct a general study on the topological properties of stretched networks. We first obtain their basic topological parameters, after that we present an optimal routing algorithm. We also present a unified approach to obtain the topological properties and the VLSI-layout of an arbitrary stretched... 

    The stretched network: Properties, routing, and performance

    , Article Journal of Information Science and Engineering ; Volume 24, Issue 2 , 2008 , Pages 361-378 ; 10162364 (ISSN) Shareghi, P ; Sarbazi Azad, H ; Sharif University of Technology
    2008
    Abstract
    In this paper, we study a class of interconnection networks for multiprocessors, called the Stretched-G network, which is based on a base graph G by replacing each edge of the base network with an array of processors. Two interesting features of the proposed topology are its area-efficient VLSI layout and superior scalability over the underlying base network while preserving most of its desirable properties. We conduct a general study on the topological properties of stretched networks. We first obtain their basic topological parameters and derive some embedding results. We then present optimal routing and broadcasting algorithms for such networks. We also present a unified approach to... 

    A 1.8V high dynamic range CMOS Gm-c filter for portable video systems

    , Article 14th International Conference on Microelectronics, ICM 2002, 11 December 2002 through 13 December 2002 ; Volume 2002-January , 2002 , Pages 38-41 ; 0780375734 (ISBN) Mehrmanesh, S ; Aslanzadeh, H. A ; Vahidfar, M. B ; Atarodi, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2002
    Abstract
    A 4th order, 5 MHz, lowpass Butterworth Gm-c filter has been combined with a low noise low-voltage amplifier to form a lowpass filter for video applications. In this filter an improved transconductor and a powerful method is used to adjust the transconductance gain for tuning application. A continuous variable gain current-to-current converter is used to tune the transconductor value. The THD of the filter is -77 dB for 1 Vppd input signal. Input referred noise is 40 nV/√Hz in the worst case. All the circuits are designed based on a 0.25 μm CMOS process technology with a single 1.8 V supply. © 2002 IEEE  

    Optimal design and performance analysis of a double-sided multi-turn wound-rotor resolver

    , Article IEEE/ASME Transactions on Mechatronics ; 2021 ; 10834435 (ISSN) Hajmohammadi, S ; Saneie, H ; Nasiri Gheidari, Z ; Tootoonchian, F ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    Multi-speed resolvers are used in the applications that need higher accuracy. However, they suffer from losing absolute position information. To overcome this challenge and improve the reliability of detecting position, using multi-turn resolvers is recommended. The conventional configuration of multi-turn resolver is using two individual resolvers on one shaft and into a common frame. Using such configuration needs special care on setting the distance between two resolvers. In this paper a new structure based on dual side configuration is proposed. The performance of the double sided resolver is analyzed and optimized using an analytical model based on magnetic equivalent circuit (MEC).... 

    A novel hardware implementation for joint heart rate, respiration rate, and gait analysis applied to body area networks

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2013 , Pages 1889-1892 ; 02714310 (ISSN) ; 9781467357609 (ISBN) Khazraee, M ; Zamani, A. R ; Hallajian, M ; Ehsani, S. P ; Moghaddam, H. A ; Parsafar, A ; Shabany, M ; Sharif University of Technology
    2013
    Abstract
    Continuous and remote monitoring of vital health-related and physical activity signs of a patient is one of the most important technology-oriented applications to monitor the health-care of ill individuals. In this paper, an innovative framework for a wireless Body Area Network (BAN) system, based on the IEEE 802.15.6 standard, with three types of sensors is proposed and implemented. These include Electrocardiogram (ECG), Force Sensitive Resistor (FSR) and Gyroscope. The proposed design is a novel implementation of an embedded system for the real-time processing and analyzing of the ECG signal, gait phases, and detection of the respiration rate from the ECG signal, by means of small... 

    Optimization of higher order pulse shapers used for reduction of noise in amplifier circuits

    , Article Scientia Iranica ; Volume 12, Issue 1 , 2005 , Pages 75-82 ; 10263098 (ISSN) Tabandeh, M ; Sharif University of Technology
    Sharif University of Technology  2005
    Abstract
    Active components in amplifiers generate noise. Thus, amplifiers too, produce noise at their output and, therefore, increase the input signal to noise ratio. This is an undesirable feature, more particularly when one is dealing with weak input signals already combined with noise. Thus, reducing amplifiers' noise becomes a necessity for some applications. To overcome this problem, one approach consists of improving electronic device technology. Another approach is the use of advanced techniques in designing low noise amplifiers by taking advantage of pulse shapers. Pulse shapers generally consist of calculated filters made of integrator(s) and differentiator(s) that limit properly the... 

    An optimal approach to synchronize non-identical chaotic circuits: An experimental study

    , Article International Journal of Circuit Theory and Applications ; Volume 39, Issue 9 , 2011 , Pages 947-962 ; 00989886 (ISSN) Naseh, M. R ; Haeri, M ; Sharif University of Technology
    Abstract
    The control signal magnitude and energy are among the limiting and therefore important factors to be addressed in the practical applications of a synchronization scheme. In this paper, we present an algorithm to find control parameters in an active sliding mode controller in order to reduce the control effort in synchronizing non-identical chaotic systems. We also determine uncertainties bound on the systems dynamics for which the calculated control parameters still guarantee the occurrence of the sliding motion of the error states. The proposed controller was practically applied on an experimental setup, consisting of two chaotic circuits, which resembles Chen and Lu systems behavior.... 

    High power amplifier based on a transformer-type power combiner in CMOS technology

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 57, Issue 11 , November , 2010 , Pages 838-842 ; 15497747 (ISSN) Javidan, J ; Atarodi, M ; Luong, H. C ; Sharif University of Technology
    2010
    Abstract
    In this brief, a transformer-type power combiner for a fully integrated high-power CMOS power amplifier (PA) is presented. The proposed power combiner is composed of a number of transformers that, unlike the ones in conventional approaches, have different sizes. This leads to higher efficiency and smaller chip area. After considering several power stage topologies, analysis and optimization of the transformer network (the power combiner) are presented. To demonstrate the advantages of the proposed architecture, a 900-MHz CMOS PA with the proposed power combiner was implemented with a 0.18-μm radio-frequency CMOS process. The amplifier achieved an efficiency value of 24% at the maximum output... 

    An area and power optimization technique for CMOS bandgap voltage references

    , Article Analog Integrated Circuits and Signal Processing ; Volume 62, Issue 2 , 2010 , Pages 131-140 ; 09251030 (ISSN) Tajalli, A ; Chahardori, M ; Khodaverdi, A ; Sharif University of Technology
    2010
    Abstract
    This article explores the main tradeoffs in design of power and area efficient bandgap voltage reference (BGR) circuits. A structural design methodology for optimizing the silicon area and power dissipation of CMOS BGRs will be introduced. For this purpose, basic equations of the bandgap circuit have been adapted such that can simply be applied in the optimization process. To improve the reliability of the designed circuit, the effect of amplifier offset has been also included in the optimization process. It is also shown that the minimum achievable power consumption and area are highly depending on the fabrication process parameters especially sheet resistivity of the available resistors in... 

    Gain boosted amplifier design for low power-high speed applications

    , Article Conference Proceedings - 2nd Annual IEEE Northeast Workshop on Circuits and Systems, NEWCAS 2004, Montreal, Que., 20 June 2004 through 23 June 2004 ; 2004 , Pages 233-235 ; 0780383222 (ISBN) Emadi, M ; Foruzandeh, B ; Farbiz, F ; Fathi, E ; Sharif University of Technology
    2004
    Abstract
    In this paper, different models of gain enhanced amplifier are compared and the most accurate one is chosen. Based on this model, complete symbolic small signal analysis is performed and a design procedure leading to high speed gain boosted amplifier is presented  

    Optimal design and performance analysis of a double-sided multiturn wound-rotor resolver

    , Article IEEE/ASME Transactions on Mechatronics ; Volume 27, Issue 1 , 2022 , Pages 493-500 ; 10834435 (ISSN) Hajmohammadi, S ; Saneie, H ; Nasiri Gheidari, Z ; Tootoonchian, F ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    Multispeed resolvers are used in the applications that need higher accuracy. However, they suffer from losing absolute position information. To overcome this challenge and improve the reliability of detecting position, the use of multiturn resolvers is recommended. The conventional configuration of multiturn resolver is using two individual resolvers on one shaft and into a common frame. Using such configuration needs special care on setting the distance between two resolvers. In this article, a new structure based on a dual side configuration is proposed. The performance of the double-sided resolver is analyzed and optimized using an analytical model based on a magnetic equivalent circuit....