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    Statistical study of nano-scale VLSI interconnect crosstalk and its induced power estimation

    , Article 2012 2nd IEEE CPMT Symposium Japan, ICSJ 2012, 10 December 2012 through 12 December 2012 ; December , 2012 ; 9781467326551 (ISBN) Mehri, M ; Sarvari, R ; Seyedolhosseini, A ; Sharif University of Technology
    2012
    Abstract
    Crosstalk due to the capacitive and inductive coupling has adverse effect on the circuit performance. In this paper crosstalk voltage and its induced power are studied for a stochastic environment bus with specific physical structure. Input switching pattern, driver, and load are swept in wide range for VLSI application to study crosstalk variation. Crosstalk and power is extracted to drive mean and standard deviation for implemented structures. The crosstalk mean and its induced power get lower with increasing of the load and driver resistance. This phenomenon is proportional to shrinking the technology  

    Single event upset immune latch circuit design using C-element

    , Article Proceedings of International Conference on ASIC, 25 October 2011 through 28 October 2011, Xiamen ; 2011 , Pages 252-255 ; 21627541 (ISSN) ; 9781612841908 (ISBN) Rajaei, R ; Tabandeh, M ; Sharif University of Technology
    2011
    Abstract
    Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in... 

    Compact modeling of dynamic trap density evolution for predicting circuit-performance aging

    , Article Microelectronics Reliability ; Volume 80 , 2018 , Pages 164-175 ; 00262714 (ISSN) Miura Mattausch, M ; Miyamoto, H ; Kikuchihara, H ; Maiti, T. K ; Rohbani, N ; Navarro, D ; Mattausch, H. J ; Sharif University of Technology
    Abstract
    It is shown that a compact MOSFET-aging model for circuit simulation is possible by considering the dynamic trap-density increase, which is induced during circuit operation. The dynamic trap/detrap phenomenon, which influences the switching performance, is also considered on the basis of well-known previous results. Stress-dependent hot-carrier effect and NBTI effect, origins of the device aging, are modeled during the circuit simulation for each device by integrating the substrate current as well as by determining the oxide-field change due to the trapped carriers over the individual stress-duration periods. A self-consistent solution can be obtained only by iteratively solving the Poisson... 

    Consistent Predictive Simulation of SRAM-Cell Performance Degradation Including Both MOSFET Fabrication Variation and Aging

    , Article 2nd IEEE Electron Devices Technology and Manufacturing Conference, EDTM 2018, 13 March 2018 through 16 March 2018 ; 2018 , Pages 31-33 ; 9781538637111 (ISBN) Gau, H ; Rohbani, N ; Maiti, T. K ; Navarro, D ; Miura-Mattausch, M ; Mattausch, H. J ; Takatsuka, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    We have developed a methodology to simulate circuit aging including the device fabrication variation with less simulation effort. As an example a 6T SRAM cell has been investigated. It is demonstrated that the variability range of the circuit performance is further enhanced due to the long-term device aging. Among the device parameters, the impurity concentration variation plays a particularly important role for the circuit performance variation. However, most sensitive for the aging degradation is the channel-length variation, because it increases the aging effect drastically. Further, the individual aging of each MOSFET is strongly dependent on the actual stress during circuit operation. ©... 

    A new variable frequency zero voltage switching control method for boost converter operating in boundary conduction mode

    , Article International Journal of Engineering, Transactions B: Applications ; Volume 33, Issue 11 , 2020 , Pages 2222-2232 Norouzi, S ; Ghoreishy, H ; Ale Ahmad, A ; Tahami, F ; Sharif University of Technology
    Materials and Energy Research Center  2020
    Abstract
    This paper proposes a new variable frequency zero voltage switching (ZVS) control method for boost converter operating in boundary conduction mode (BCM). The intended method keeps the converter in BCM despide of the load and input voltage variations. This is done by changing switching frequency in a certain specified range. The proposed method can guarantee circuit performance in BCM via zero-crossing detection of the inductor current and changing the switching frequency. In addition, with a slight modification in control structure, it is possible to achieve a fully ZVS in all cases. This converter control is carried out in analog form without using microprocessors which, compared with the... 

    A compact mixer and DAC for implementation of a direct conversion OQPSK transmitter

    , Article 2007 IEEE Region 10 Conference, TENCON 2007, Taipei, 30 October 2007 through 2 November 2007 ; 2007 ; 1424412722 (ISBN); 9781424412723 (ISBN) Chahardori, M ; Mehrmanesh, S ; Zamanlooy, B ; Atarodi, M ; Sharif University of Technology
    2007
    Abstract
    A compact low power circuit for implementation of a direct conversion OQPSK modulator is proposed. The circuit consists of a digital to analog converter, a low pass filter and an up-converter mixer. By embedding these three blocks, the circuit performance is enhanced and the total power consumption is reduced. The mixer is designed base on a Gilbert cell with on chip inductor loads. Instead of transconductance transistors of Gilbert cell, a fully deferential current mode DAC is used and proficiently a low pass filter is embedded between them and therefore the linearity of total system is improved. All of circuits are designed based on 0.18 μm CMOS technology with a single 1.8 volt power...