Sharif Digital Repository

We present an LC circuit model that supports a tilted “Dirac cone” in its spectrum. The tilt of the Dirac cone is specified by the parameters of the model consisting of mutual inductance between the neighboring sites and a capacitance C0 at every lattice site. These parameters can be completely measured by impedance spectroscopy. Given that a tilted Dirac cone can be described by a background spacetime metric, the impedance spectroscopy can perfectly provide (local) information about the metric of the spacetime. Nonuniform spatial dependence of the mutual inductance or capacitance induces a nontrivial geometrical structure on the emergent spacetime. Our work extends the range of usefulness... 

In this paper we analyses the energy consumption of well known family of asynchronous circuits and present a new methodology for energy estimation of these circuits at intermediate-level of abstraction. Energy estimation is performed by simulating the intermediate format of the design. The number of Read and Write accesses on the ports of the concurrent processes are counted by analyzing the conditional and computational portion during the simulation which is the base of our estimation methodology. Our proposed power estimation scheme is faster than usual post-synthesis power estimation by an order of 9, while the estimated power resides in a boundary of 11% total imprecision. © 2007 IEEE  

The interinjection locking of microwave oscillators is investigated using differential equations governing the locking behaviour of two mutually coupled oscillators. The behaviour of the oscillators before and after locking is described, and the common oscillation frequencies, locking range and transient time constant are calculated. The spectra of the oscillators in the unlocked condition are also investigated, with particular attention to the spacing and amplitude variation of the spectral lines. Experimental results in connection with the theoretical investigations are also presented  

In search of low cost and flexible substrates organic transistors have been suggested as an alternate to silicon transistors. Level 1 model extraction, investigating different circuit styles and proposing two new circuit styles for organic integrated circuits is done in this paper. First, level 1 model of organic transistor is found using ID-VDS characteristics of transistors reported by [9]. After that different design styles used in CMOS digital integrated circuits are reviewed and the functionality of these styles for organic integrated circuits is investigated. Two new circuit styles have been proposed in this section which have better performance for organic circuits comparing with... 

In this paper, we propose a novel approach to extract a network of half adders from the gate-level net-list of an addition circuit while no internal equivalences exist. The technique begins with a gatelevel net-list and tries to map it into word-level adders based on an efficient bit-level adder representation. It will be shown that the proposed technique is suitable for several gate-level architectures of multipliers, as it extracts adder components in a step-wise method. This approach can also be generalized to other arithmetic circuits. In order to evaluate the effectiveness of our approach, we run it on several arithmetic circuits and compare experimental results with those of... 

The switch level is an abstraction level between the gate level and the electrical level, offers many advantages. Switch level simulators can reliably model many important phenomena in CMOS circuits, such as bi-directional signal propagation, charge sharing and variations in driving strength. However, the fault simulation of switch level models is more time-consuming than gate level models. This paper presents a method for fast fault emulation of switch level circuits using FPGA chips. In this method, gates model switch level circuits and we can emulate mixed gate-switch level models. By the use of this method, FPGA chips can be used to accelerate the fault injection campaigns into switch... 

Modified two-phase latch and flip-flop are introduced to implement a linear phase-detector (LPD) for 1/N-rate clock recovery applications. This technique greatly simplifies the required circuitry of the LPD and makes it suitable for higher speed applications while consuming less power compared to the conventional techniques  

This paper presents a low-voltage, CMOS-compatible, voltage-mode structure for multiple-valued logic circuits. Designed based on a simple and straightforward mechanism and operating in the voltage mode, the proposed structure is suitable for low power applications. Design of both a quaternary inverter and a latch circuit based on the proposed structure are also presented. These circuits are designed in a 0.18-μm CMOS technology with a supply voltage of 1.8V, and dissipate 60nW static power for both circuits. Static noise margin of the inverter is 0.22V  

In this work we introduce new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of Vdd=0.1-1.5V and Vth=0-0.8V, are analyzed to find optimal Vdd and Vth BSIMSOI3.3 model (level 57) is used to verify the answers. We show that Energy-Delay Product (EDP) isn't appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and... 

High frequency transformer is an important component in lots of modern power electronic circuits. In order to analyze the behavior of these transformers, equivalent circuit models containing parasitic elements have been proposed. But most of them are complicated and not appropriate to use in processes in which high speed analysis is crucial. In this paper, a second-order simplified model for high frequency transformers is obtained. Besides, the frequency ranges in which the proposed model has enough precision, are calculated and examined. To validate the simplified circuit model, some simulations are carried out. During the simulation, the effects of transformer equivalent circuit parameters... 

In this paper, different models of gain enhanced amplifier are compared and the most accurate one is chosen. Based on this model, complete symbolic small signal analysis is performed and a design procedure leading to high speed gain boosted amplifier is presented  

This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

During the last years several logic styles have been proposed to counteract power analysis attacks. This article starts with a brief review of four different logic styles namely RSL, MDLP, DRSL, and TDPL. This discussion continues to examine the effect of the number of fanouts in power consumption of a CMOS inverter. Moreover, it is shown that insertion of delay elements in typical CMOS circuits is not adequate to prevent the glitches and information leakage unless the fanouts of input signals are balanced. Whereas enable signals have to be classified according to the depth of combinational circuits implemented using pre-charge logic styles, we show that the number of fanouts of enable... 

A structured design of Subscriber Line Interface System and Circuit will be described. A high level synthesis allows extracting overall system and circuit requirements to satisfy the desired specifications, standards, and a robust implementation. For this purpose, first the output driving stage will be analyzed and then, dc, ac, and longitudinal balance feedbacks will be considered. Then based on extracted system specifications, optimum circuit design of line-driver will be described. High-level design of line-driver as the most important circuit block optimized for stability, accuracy, area, and power dissipation will be elaborated  

Nickel modified NiOOH electrodes were used for the electrocatalytic oxidation of ethanol in alkaline solutions. The electro-oxidation of ethanol in a 1 mol/L NaOH solution at different concentrations of ethanol was studied by ac impedance spectroscopy. Electrooxidation of ethanol on Ni shows negative resistance on impedance plots. The impedance shows different patterns at different applied anodic potential. The influence of the electrode potential on impedance was studied and a quantitative explanation for the impedance of ethanol oxidation was given by means of a proposed mathematical model. At potentials higher than 0.52 V(vs. Ag/AgCl), a pseudoinductive behavior was observed, but at those... 

A novel BiCMOS voltage-to-voltage converter with logarithmic characteristics and very high accuracy is presented. The relationship between the emitter current and the base-emitter voltage in bipolar transistors is used to realize the logarithmic function. With 1.8 supply voltage, the total power consumption is less than 15.75 mW and a Log error of < -36dB is shown in the ADS simulations. Compared to the other method in the literature, very better accuracy in logarithm calculation is achieved. The proposed method can be used in arithmetical operation circuits like analog processors  

One of the most prominent issues in fully adiabatic circuits is the breaking reversibility problem; i.e., non-adiabatic energy dissipation in the last stage adiabatic gates whose outputs are connected to external circuits. In this paper, we show that the breaking reversibility problem can result in significant energy dissipation. Subsequently, we propose an efficient technique to address the breaking reversibility problem, which is applicable to the usual fully adiabatic logic such as 2LAL, SCRL, and RERL. Detailed SPICE simulations are used to evaluate the proposed technique. The experimental results show that the proposed technique can considerably reduce (e.g., about 74% for RERL, 35% for... 

Security in mobile handsets of telecommunication standards such as GSM, Project 25 and TETRA is very important, especially when governments and military forces use handsets and telecommunication devices. Although telecommunication could be quite secure by using encryption, coding, tunneling and exclusive channel, attackers create new ways to bypass them without the knowledge of the legitimate user. In this paper we introduce a new, simple and economical circuit to warn the user in cases where the message is not encrypted because of manipulation by attackers or accidental damage. This circuit not only consumes very low power but also is created to sustain telecommunication devices in aspect... 

A circuit model has been proposed for two-dimensional metallic arrays of metallic square holes located on a homogeneous substrate. Although the proposed circuit model holds true, the surface admittance between the metallic hole array and the cover was erroneously calculated since the presence of the cross-polarization terms had been neglected. Furthermore, there have been mistakes in numerical simulation and in analytical calculations based on the presented formulas. The correct formulation is now given, and erroneous figures are replotted  

In parallel with enhancements in the technology of integrated circuits, transistors are implemented in silicon. Though the price is reduced; design is more complicated, which create the efficiency and power consumption. The reason why modern GDI-based circuit is the focus of attention is that in designing digital circuit, less power is required while more efficiency is obtained. Lowering the complexity of logic circuit can bring about reduction of power consumption, propagation delay and decrease circuit space. GDI-based integrated circuit resembles MOSFET transistors but have fewer transistors and higher performance capability. This study addresses two main areas which are Studying and...