Sharif Digital Repository

In this paper, design and analysis using analytical expressions for the inverse class-E power amplifier (PA) operating at the outside nominal operation, i.e., class-En PA, is presented. This operation is defined as non-zero current switch (n-ZCS) and non-zero derivative current switch (n-ZDCS) conditions. The generalized design equations as a function of design specifications, load-resistance and a given dc-supply voltage are derived. Two degrees of the design freedom achieved thanks to n-ZCS and n-ZDCS that are utilized for the simultaneous satisfaction of design specifications, such as peakswitch- voltage and peak-switch-current along with a given loadresistance. The output power... 

The Class-E power amplifier has been widely studied and formulated in the literature. Although the majority of reported inductive coupling wireless power transfer (WPT) systems use a class-E power amplifier for driving the primary coil, still there is a lack of a comprehensive study on class-E circuit dedicated to WPT, providing a set of closed form design equations for proper class-E operation. This paper presents the required design equations needed to design a 'true' class-E circuit for WPT applications. Equations for the series-tuned secondary coil WPT system are presented, as well as two different design procedures for the parallel-tuned secondary coil. The derived equations have been... 

In this paper, design and analysis using analytical expressions for the inverse class-E power amplifier (PA) operating at the outside nominal operation, i.e., class- $ ext{E}-{mathrm{n}}$ PA, is presented. This operation is defined as nonzero current switch (n-ZCS) and nonzero-derivative-current switch (n-ZDCS) conditions. The generalized design equations as a function of design specifications, load resistance, and a given dc-supply voltage are derived. Two degrees of the design freedom achieved thanks to n-ZCS and n-ZDCS that are utilized for the simultaneous satisfaction of design specifications, such as peak-switch-voltage and peak-switch-current along with a given load resistance. The... 

In this paper, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the... 

In this brief, the switching behavior of the cascode topology is improved through the floating bulk (FB) technique. Although the cascode structure has the advantage of reducing voltage stress on transistors, its parasitic elements increase power loss. The FB technique has been proposed to alleviate the power loss in the cascode class-E PA topology which results in enhancement of power added efficiency (PAE). In this method, the bulk of the common-gate (CG) transistor is connected to the ground through a resistor. As a result, the parasitic capacitances between the drain and source of the CG transistor create a new path of current that accelerates charging of parasitic capacitance at the...