Sharif Digital Repository

In this thesis, A novel approach for ¼-rate clock Phase Detector (PD) structure for Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) is proposed. In this approach, the retimed data is generated within the circuit and no extra circuit is needed. Another advantage of this topology is that the error and reference signals are independent of delay time through gates and no extra replica circuit is needed to compensate the delay. This topology results in a lower power circuit and smaller area for high speed application compared to conventional topologies  

Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been... 

Some applications need fast locking clock and data recovery circuits for example the circuits that operate in burst mode must lock to the data packets which are transmitting from different transmitters very quickly and in just a few bit times. In such applications open-loop clock and data recovery circuits are used because lock time in closed-loop clock and data recovery circuits is usually much longer.
In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider... 

The continuous growth of network traffic and people's demand for higher data rates, have driven wireline communication systems towards higher data rates. In these systems, the power consumption of these transmitters and receivers is a crucial and influential factor. This paper presents two different solutions to reduce the power consumption and area of these systems. In the first solution, a low-power phase shifter with variable phase and amplitude control is introduced. The changes in these parameters are mutually orthogonal, ensuring that a change in one characteristic does not affect the others. This phase shifter can be used to generate clock pulses with different phases in wireline...