Sharif Digital Repository

A new family of sampled-data filters in which accuracy is a function of the ratio of the resistors is introduced. It is shown that this structure is suitable for low-voltage high-speed applications. A biquad filter with a quality factor of 10 and a clock frequency of 60MHz consuming only 2mW power is also presented  

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μ CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA... 

Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

A novel N-path filter using a complex impedance is designed to replace the frontend SAW filters in receivers with on-chip bandpass filters. It is demonstrated that the center frequency of the filter can be tuned solely by changing the value of some capacitances without the need to change the clock frequency. In addition, thanks to the use of smaller capacitors, the silicon area is reduced compared to similar designs. The high-Q bandpass filter is realized utilizing two gyrators and an arrangement of four baseband capacitors with NMOS switches, driven by 4-phase 25% duty cycle clock signals. This paper also analyzes the performance of the proposed filter against imperfections such as thermal... 

This paper introduces "switched-resistor" circuits as a new family of current-mode sampled-data circuits with improved accuracy and linearity. Advantages of the switched-resistor circuits for high-speed and low-voltage applications are demonstrated. A switched-resistor biquad band-pass filter with a quality factor of 10 and clock frequency of 100 MHz, fabricated in a 0.18 μ m CMOS process, is also presented. The filter consumes 9 mW from 1.8 V supply. © 2008 Elsevier GmbH. All rights reserved  

This paper introduces a novel scalable pipelined VLSI architecture for a 4×4 64-QAM hard-output multiple-input-multiple-output (MIMO) detector based on K-best lattice decoders. The key contribution is a means of expanding the intermediate nodes of the search tree on-demand, rather than exhaustively, along with three types of distributed sorters operating in a pipelined structure. The proposed architecture has a fixed critical path independent of the constellation size, on-demand expansion scheme, efficient distributed sorters, and is scalable to higher number of antennas. Fabricated in 0.13 μCMOS, it occupies 0.95 μ mm} 2 core area. Operating at 282 MHz clock frequency, it dissipates 135 mW... 

RSA based SmartCards have been widely used in security services such as secure data transmission in many applications over the past few years. Generation of a secure key pair which is based on finding a pair of large prime numbers is an indispensable part of creating a secure channel. This paper describes a novel approach for secure and fast key generation of the public key cryptographic algorithm of RSA. This method has been implemented on a typical SmartCard equipped with a crypto-coprocessor and a true random number generator. An efficient method for generating the large random prime numbers is proposed that considerably reduces the total time required for generating a key pair. The key... 

A dual mode UHF RFID transponder in 0.18 μm CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog and digital blocks enables the chip to operate with a 1 V regulated voltage and thus to reduce the power consumption. The novel dual mode architecture enables the chip to work in passive and battery-assisted modes controlled by the reader. A custom Gen 2 based command switches the operation mode of the circuit. By using a special clock calibration method the chip operates from 1.2 to 5 MHz clock frequency. Several low power techniques are employed to reduce the power consumption of the chip which is essential in passive RFID tags. Measurement results show that... 

In this paper, Stochastic Activity Networks (SANs) are exploited to model and evaluate the power consumption and performance of virtualized servers in cloud computing. The proposed SAN models the physical servers in three different power consumption and provisioning delay modes, switching the status of the servers according to the workload of the corresponding cluster if required. The Dynamic Voltage and Frequency Scaling (DVFS) technique is considered in the proposed model for dynamically controlling the supply voltage and clock frequency of CPUs. Thus, Virtual Machines (VMs) on top a physical server can be divided into several power consumption and processing speed groups. According to the...