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      Compact, low-voltage, low-power and high-bandwidth CMOS four-quadrant analog multiplier

      , Article 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010, Gammarth ; 2010 ; 9781424468164 (ISBN) Ebrahimi, A ; Miar Naimi, H ; Gholami, M ; Sharif University of Technology
      2010
      Abstract
      In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD  
    Total 1 records