Search for: cmos-processs
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    Ultra high-throughput architectures for hard-output MIMO detectors in the complex domain

    , Article Midwest Symposium on Circuits and Systems, 7 August 2011 through 10 August 2011l ; August , 2011 ; 15483746 (ISSN) ; 9781612848570 (ISBN) Mahdavi, M ; Shabany, M ; Sharif University of Technology
    In this paper, a novel hard-output detection algorithm for the complex multiple-input multiple-output (MIMO) detectors is proposed, which results in a significant throughput enhancement, a near-ML performance, and an SNR-independent fixed-throughput. Moreover, a high-throughput VLSI implementation is proposed, which is based on a novel method of the node generation and sorting scheme. The proposed design achieves the throughput of 10Gbps in a 0.13 μ CMOS process, which is the highest throughput reported in the literature for both the real and the complex domains. Synthesis results in 90nm CMOS also show that the proposed scheme can achieve the throughput of up to 15Gbps. Moreover, the FPGA... 

    Wireless interfacing to cortical neural recording implants using 4-FSK modulation scheme

    , Article IEEE International Conference on Electronics, Circuits, and Systems, 6 December 2015 through 9 December 2015 ; Volume 2016 March , 2016 , Pages 221-224 ; 9781509002467 (ISBN) Eslampanah Sendi, M. S ; Judy, M ; Molaei, H ; Sodagar, A. M ; Sharifkhani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc 
    This paper used a 4-level frequency shift keying (4-FSK) modulation scheme to enhance the density of wireless data transfer from implantable biomedical microsystems to the outside world. Modeling and simulation of the wireless channel for 4-FSK modulation in the case of a neural recording implant has been done. To realize the 4-FSK scheme, the modulator and demodulator circuits are proposed, designed and simulated in a 0.18-μm CMOS process, and in the 174-216 MHz frequency band at a data rate of 13.5 Mbps. Operated using a 1.8 V supply voltage, the modulator circuit consumes a power of 7.8 μW  

    Low voltage low power 8-bit folding/interpolating ADC with rail-to-rail input range

    , Article Analog Integrated Circuits and Signal Processing ; Volume 61, Issue 2 , 2009 , Pages 181-189 ; 09251030 (ISSN) Movahedian Attar, H ; Sharif Bakhtiar, M ; Sharif University of Technology
    A new technique for improving the performance of low-voltage folding ADC's by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input-output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power... 

    Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology

    , Article International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN) Javidan, J ; Atarodi, S. M ; Luong, H. C ; Sharif University of Technology
    Wiley  2012
    This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including... 

    Compact, low-voltage, low-power and high-bandwidth CMOS four-quadrant analog multiplier

    , Article 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010, Gammarth ; 2010 ; 9781424468164 (ISBN) Ebrahimi, A ; Miar Naimi, H ; Gholami, M ; Sharif University of Technology
    In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD  

    High power amplifier based on a transformer-type power combiner in CMOS technology

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 57, Issue 11 , November , 2010 , Pages 838-842 ; 15497747 (ISSN) Javidan, J ; Atarodi, M ; Luong, H. C ; Sharif University of Technology
    In this brief, a transformer-type power combiner for a fully integrated high-power CMOS power amplifier (PA) is presented. The proposed power combiner is composed of a number of transformers that, unlike the ones in conventional approaches, have different sizes. This leads to higher efficiency and smaller chip area. After considering several power stage topologies, analysis and optimization of the transformer network (the power combiner) are presented. To demonstrate the advantages of the proposed architecture, a 900-MHz CMOS PA with the proposed power combiner was implemented with a 0.18-μm radio-frequency CMOS process. The amplifier achieved an efficiency value of 24% at the maximum output... 

    An analytical model for soft error critical charge of nanometric SRAMs

    , Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 17, Issue 9 , 2009 , Pages 1187-1195 ; 10638210 (ISSN) Jahinuzzaman, S. M ; Sharifkhani, M ; Sachdev, M ; Sharif University of Technology
    Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus...