Sharif Digital Repository

In this paper the design of a digital step attenuator with simultaneous low phase and gain error characteristics is investigated. First, the loading effect of the consecutive blocks of an N-bit attenuator on the precision of the attenuation levels is analyzed. Then a modified structure to decrease the loading effect as well as the phase error of the attenuator blocks is presented. A comprehensive analysis of the circuit is performed and some design guidelines have described. Finally, a 6-bit attenuator with attenuation range of 0.5–31.5 dB and resolution of 0.5 dB is implemented in 0.18 µm complementary metal–oxide-semiconductor (CMOS) technology. The root mean square (RMS) gain error and... 

A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. A new switched-network topology has been proposed for implementing the 5.625 ° phase shift step. The insertion loss of the circuit is compensated with an on-chip bidirectional amplifier. The measured return losses of the circuit are better than 8 dB with output 1-dB compression point of +9.5 dBm in the transmit mode and noise figure of 7.1 dB in the receive mode. The fabricated phase shifter demonstrates an average rms phase error of less than 2° over the entire operation bandwidth, which makes it suitable for high-precision applications