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    A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer

    , Article APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30 November 2008 through 3 December 2008 ; 2008 , Pages 1383-1386 ; 9781424423422 (ISBN) Saeedi, S ; Atarodi, M ; Sharif Bakhtiar, M ; Sharif University of Technology
    2008
    Abstract
    A divide-by-3 frequency divider for Inphase and Quadrature (I/Q) LO signal generation in a multi-band frequency synthesizer is presented. Using divisor numbers other than powers of 2 (2n) for quadrature signal generation, reduces the required frequency range of the VCO in multi-band frequency synthesizers. The divide-by-3 circuit is designed in a 0.18um CMOS technology. © 2008 IEEE  

    A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology

    , Article Microelectronics Journal ; Volume 90 , 2019 , Pages 48-57 ; 00262692 (ISSN) Heydarzadeh, S ; Torkzadeh, P ; Sadughi, S ; Sharif University of Technology
    Elsevier Ltd  2019
    Abstract
    A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The... 

    12 bits, 40MS/s, low power pipelined SAR ADC

    , Article Midwest Symposium on Circuits and Systems ; Aug , 2014 , p. 841-844 Khojasteh Lazarjan, V ; Hajsadeghi, K ; Sharif University of Technology
    Abstract
    This paper presents a low power SAR ADC utilizing pipelining to increase the resolution up to 12 bits while maintaining a high speed sampling rate. Novel system level modifications and also new comparator architecture are proposed to optimize the power consumption. The ADC is designed and simulated in 0.18um CMOS technology by 1.2v supply voltage consuming 4.5mW power at 40MS/s sampling rate. The results indicates an effective number of bits (ENOB) of 11.04 bit and a challenging FOM of 54.9 fj/conversion which verifies the competence of proposed method  

    A method for noise reduction in active-rc circuits

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 58, Issue 12 , 2011 , Pages 906-910 ; 15497747 (ISSN) Gharibdoust, K ; Bakhtiar, M. S ; Sharif University of Technology
    Abstract
    A method for noise reduction in active-$RC$ circuits is introduced. It is shown that the output noise in an active-$RC$ circuit can be considerably reduced, without disturbing the circuit transfer function by inserting appropriate passive or active components in the circuit. The inserted components introduce new signal paths in the circuit for noise reduction while the original circuit transfer function is kept unchanged. The procedure to define the proper paths in the circuit and their transfer functions is given. The effectiveness of the presented method is demonstrated using a second-order active-RC filter fabricated in a 0.18-$ {m}$ CMOS technology  

    A novel nano-scaled SRAM cell

    , Article World Academy of Science, Engineering and Technology ; Volume 65 , 2010 , Pages 172-174 ; 2010376X (ISSN) Azizi Mazreah, A ; Sahebi, M. R ; Manzuri Shalmani, M. T ; Sharif University of Technology
    Abstract
    To help overcome limits to the density of conventional SRAMs and leakage current of SRAM cell in nanoscaled CMOS technology, we have developed a four-transistor SRAM cell. The newly developed CMOS four-transistor SRAM cell uses one word-line and one bit-line during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 19% smaller than a conventional six-transistor cell using same design rules. Also the leakage current of new cell is 60% smaller than a conventional sixtransistor SRAM cell. Simulation result in 65nm CMOS technology shows new cell has correct operation during read/write operation and idle mode  

    Design and Implementation of Protected Smart High Side and Low Side Switch and Drivers in 0.18um HV BCD CMOS Technology

    , M.Sc. Thesis Sharif University of Technology Kachuee, Sajjad (Author) ; Medi, Ali (Supervisor) ; Zolghadri, Mohammad Reza (Supervisor)
    Abstract
    In this thesis, two types of smart switch & driver chips are designed in 0.18 um HV BCD technology; low side driver and high side driver. These drivers are smart, because of having various types of protection and detection circuits, which protect switch, driver and connected load, versus errors that can be occurred by the user or other environmental effects. The protection circuits are battery over & under voltage shutdown, current limit, inductive load clamper and thermal shutdown. Load status is checked by status detection circuit and reported to user by one bit flag. Battery voltage can vary from 7 V to 40 V and output current is limited to 2 A. Designed high side and low side drivers are... 

    A low complexity architecture for the cell search applied to the LTE systems

    , Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, 9 December 2012 through 12 December 2012 ; Dec , 2012 , Pages 300-303 ; 9781467312615 (ISBN) Golnari, A ; Sharifan, G ; Amini, Y ; Shabany, M ; Sharif University of Technology
    2012
    Abstract
    Cell search is a crucial process in the synchronization procedure for the 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) system. In this paper, a high-speed, low-complexity and reliable architecture is proposed for both steps of cell search: sector ID and cell ID group detection. For the sector ID detection, two novel methods, sign-bit reduction and wise resource sharing, are proposed. In addition, for the cell ID group detection, we proposed an algorithm based on the Maximum Likelihood Sequence Detection (MLSD) called 'sign-bit MLSD'. Simulations show that the proposed methods result in more than 90% reduction in area compared to the state-of-the-art. We designed and... 

    A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18μm CMOS

    , Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, Seville, Seville, 9 December 2012 through 12 December 2012 ; 2012 , Pages 157-160 ; 9781467312615 (ISBN) Jalili, H ; Fotowat Ahmady, A ; Jenabi, M ; Sharif University of Technology
    2012
    Abstract
    A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using... 

    New operational transconductance amplifiers using current boosting

    , Article Midwest Symposium on Circuits and Systems ; 2012 , Pages 109-112 ; 15483746 (ISSN) ; 9781467325264 (ISBN) Noormohammadi, M ; Lazarjan, V. K ; HajSadeghi, K ; Sharif University of Technology
    2012
    Abstract
    New techniques for Class-AB Operational Transconductance Amplifiers (OTAs) are presented. These new techniques are two topologies based on current boosting in class-AB stage which achieve considerable improvement of Slew Rate and Gain-Bandwidth while maintaining the same power consumption as the conventional design. Circuit level analysis and simulation results of proposed circuits in 0.18μm CMOS technology for gain, GBW, slew rate, and settling time are presented to prove the effectiveness of the proposed design method  

    Down-conversion self-oscillating mixer by using CMOS technology

    , Article Proceedings - 2012 IEEE 8th International Colloquium on Signal Processing and Its Applications, CSPA 2012 ; 2012 , Pages 33-36 ; 9781467309615 (ISBN) Kouchaki, M ; Zahedi, A ; Sabaghi, M ; Ameri, S. R. H ; Niyakan, M ; Sharif University of Technology
    2012
    Abstract
    In this paper a self-oscillating mixer is presented fundamental signal generated by the oscillator subcircuit in the mixing process. The oscillator core consumes 3mA of current from a 1.8 V DC supply and results in an output power of -0.867 dBm per oscillator, and a measured phase noise of -91, -102 and -108 dBc/Hz at 100 KHz, 600 KHz and 1 MHz from the carrier, respectively. In the mixing process the proposed mixer achieved IIP3 of 0 dBm with conversation gain of 1.93 dB. The circuit was designed and simulated in 0.18-μm CMOS technology by ADS2010  

    A low-power current reuse CMOS RF front-end for GPS applications

    , Article 2011 IEEE International RF and Microwave Conference, RFM 2011 - Proceedings, 12 December 2011 through 14 December 2011, Seremban ; 2011 , Pages 416-419 ; 9781457716294 (ISBN) Jalili, H ; Fotowat Ahmady, A ; Sharif University of Technology
    Abstract
    A very low-power RF front-end based on a new current reuse QLMV cell (Quadrature VCO-LNA-Mixer) is proposed for GPS applications. The front-end, designed in 0.18μm CMOS technology, provides improved performance characteristics while consuming only 1 mA current. Simulation results are presented and compared with recently published works in the field  

    Single event upset immune latch circuit design using C-element

    , Article Proceedings of International Conference on ASIC, 25 October 2011 through 28 October 2011, Xiamen ; 2011 , Pages 252-255 ; 21627541 (ISSN) ; 9781612841908 (ISBN) Rajaei, R ; Tabandeh, M ; Sharif University of Technology
    2011
    Abstract
    Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in... 

    New configuration memory cells for FPGA in nano-scaled CMOS technology

    , Article Microelectronics Journal ; Volume 42, Issue 11 , 2011 , Pages 1187-1207 ; 00262692 (ISSN) Azizi Mazreah, A ; Manzuri Shalmani, M. T ; Sharif University of Technology
    2011
    Abstract
    In nano-scaled CMOS technology, the reduction of soft error rate and leakage current are the most important challenges in designing Field Programmable Gate Arrays (FPGA). To overcome these challenges, based on the observations that most configuration bit-streams of FPGA are zeros across different designs and that configuration memory cells are not directly involved with signal propagation delays in FPGA, this paper presents three new low-leakage and hardened configuration memory cells for nano-scaled CMOS technology. These cells are completely hardened when zeros are stored in the cells and cannot flip from particle strikes at the sensitive cell nodes. These cells retain their data with... 

    A 6-bit active digital phase shifter

    , Article IEICE Electronics Express ; Volume 8, Issue 3 , 2011 , Pages 121-128 ; 13492543 (ISSN) Asoodeh, A ; Atarodi, M ; Sharif University of Technology
    2011
    Abstract
    This paper presents the design of a 6-bit active digital phase shifter in 0.18-μm CMOS technology. The active phase shifter synthesizes the required phase using a phase interpolation process by adding quadrature phased input signals. It uses a new quadrature all-pass filter for quadrature signaling with a wide bandwidth and low phase error. The phase shifter has simulated RMS phase error of <0.85° at 2.4-5 GHz. The average voltage gain ranges from 1.7 dB at 2.4GHz to -0.14 dB at 5 GHz. Input P1 dB is typically 1.3±0.9 dBm at 3.5 GHz for overall phase states  

    A compact 8-bit AES crypto-processor

    , Article 2nd International Conference on Computer and Network Technology, ICCNT 2010, 232010 through 25 April 2010 ; April , 2010 , Pages 71-75 ; 9780769540429 (ISBN) Haghighizadeh, F ; Attarzadeh, H ; Sharifkhani, M ; Sharif University of Technology
    2010
    Abstract
    Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standard-cell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far  

    A fully integrated 0.18-μm CMOS transceiver chip for X-band phased-array systems

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 60, Issue 7 , 2012 , Pages 2192-2202 ; 00189480 (ISSN) Gharibdoust, K ; Mousavi, N ; Kalantari, M ; Moezzi, M ; Medi, A ; Sharif University of Technology
    Abstract
    An X-band core chip is designed and fabricated in 0.18-μm CMOS technology, which can significantly reduce the monolithic microwave integrated circuit count required for realizing an active beam-former T/R module. The core chip consists of two RX/TX paths, each of which includes a 6-b phase shifter, a 6-b attenuator, along with two input and output amplifiers. A new architecture for realizing such a core chip system and a low loss circuit for 5.625° phase shift block are proposed. The overall rms phase and gain errors are better than 2° and 0.25 dB, respectively, in both RX/TX paths. The gain of each path is around 12 dB, while the output 1-dB compression point is higher than 10 dBm over the... 

    An audio band low voltage CT-ΔΣ modulator with VCO-based quantizer

    , Article 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 232-235 ; 9781457718458 (ISBN) Yousefzadeh, B ; Sharifkhani, M ; Sharif University of Technology
    Abstract
    This paper presents the design and implementation of a low power, low voltage, continuous time delta sigma modulator for audio band in 90 nm CMOS technology. A VCO-based integrator and quantizer are used. Inherent dynamic element matching (DEM) of the quantizer eliminates the need for explicit DEM logic which results in a short excess-delay and power saving. Simulation results show that the modulator achieves 78 dB SNDR and 87 dB SNR in a 20 kHz input bandwidth and dissipates 106 μW from 1 V supply. The power consumption for different parts is discussed  

    A noise shaped flash time to digital converter for all digital frequency synthesizers

    , Article ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, 23 August 2009 through 27 August 2009 ; 2009 , Pages 898-901 ; 9781424438969 (ISBN) Ensafdaran, M ; Atarodi, M ; Sharif University of Technology
    Abstract
    Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise  

    A 5.3ps 8b Time to digital converter using a new gain-reconfigurable time amplifier

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; 2018 ; 15497747 (ISSN) Molaei, H ; Hajsadeghi, K. H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2018
    Abstract
    Time amplifiers (TA) are the key building blocks of the two-step time-to-digital converters. High resolution TAs suffer from inaccuracy the gain due to employing meta-stability behavior of the SR latches. In the proposed method, two offset NAND gates are placed in parallel with the NAND gates of the conventional SR latch to get a linear re-configurable gain. Gain of the TA is controlled only by the driving strength of the NAND gates. To confirm the effectiveness of the proposed method, an 8-bit two step time to digital converter (TDC) was designed and laid-out in 0.18 μ m CMOS technology. Using a supply voltage of 1.2V, the proposed TDC consumes 1.1mW at 30MS/s throughput. IEEE  

    Design of a 2-12-GHz bidirectional distributed amplifier in a 0.18- mu m CMOS technology

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 2 , 2019 , Pages 754-764 ; 00189480 (ISSN) Alizadeh, A ; Meghdadi, M ; Yaghoobi, M ; Medi, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- boldsymbol mu ext{m} CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ( n-{ ext {opt}} ), maximum achievable power gain ( G-{P} ), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., n ) is offered where dc-power consumption of the circuit ( P-{ ext {dc}} ) is also considered. This formula optimizes G-{P}/P-{ ext {dc}} , and it is preferred over the conventional n-{ ext {opt}} formula. To validate the theoretical analyses, a 2-12-GHz BDDA with high output 1-dB...