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Fast reliability analysis method for sequential logic circuits
, Article Proceedings - ICSEng 2011: International Conference on Systems Engineering, 16 August 2011 through 18 August 2011, Las Vegas, NV ; 2011 , Pages 352-356 ; 9780769544953 (ISBN) ; Jahanirad, H ; Attarsharghi, P ; Sharif University of Technology
2011
Abstract
Reliability analysis of combinational logic circuits using error probabilities methods, such as PTM, has been widely developed and used in literature. However, using these methods for reliability analysis of sequential logic circuits will lead to inaccurate results, because of existence of loops in their architecture. In this paper a new method is proposed based on converting the sequential circuit to a secondary combinational circuit and applying an iterative reliability analysis to the resulting configuration. Experimental results demonstrate good accuracy levels for this method